V2Va: An Efficient Verilog-to-Verilog-A Translator for Accelerated Mixed-Signal Simulation

Yicong Shao; Chao Wang; Jiajie Huang; Wangzilu Lu; Zhiwen Gu; Longfan Li; Yuhang Zhang; Jian Zhao; Wei Mao; Yongfu Li

doi:10.1109/APCCAS60141.2023.00058

V2Va: An Efficient Verilog-to-Verilog-A Translator for Accelerated Mixed-Signal Simulation

Yicong Shao
, Chao Wang
, Jiajie Huang
, Wangzilu Lu
, Zhiwen Gu
, Longfan Li
, Yuhang Zhang
, Jian Zhao
, Wei Mao
, Yongfu Li^*

^*此作品的通讯作者

Shanghai Jiao Tong University
Hangzhou Institute of Technology

科研成果: 书/报告/会议事项章节 › 会议稿件 › 同行评审

2 引用（Scopus）

摘要

This paper introduces a streamlined Verilog-to-Verilog-A (V2Va) translation tool that automates the conversion of Verilog designs into Verilog-A, enabling concurrent simulation of analog and digital circuits. Through a set of mapping rules, V2Va facilitates mixed-signal simulations in an analog environment, negating the requirement for a separate mixed-signal simulation engine and overcoming multiple types of EDA licensing obstacles. Our methodology demonstrates a notable acceleration in mixed-signal simulation, surpassing 2 ×, underscoring its significant impact and applicability in the domain of circuit design.

源语言	英语
主期刊名	Proceedings - 2023 19th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2023
出版商	Institute of Electrical and Electronics Engineers Inc.
页	222-226
页数	5
ISBN（电子版）	9798350381191
DOI	https://doi.org/10.1109/APCCAS60141.2023.00058
出版状态	已出版 - 2023
已对外发布	是
活动	19th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2023 - Hyderabad, 印度期限: 19 11月 2023 → 22 11月 2023

出版系列

姓名	Proceedings - 2023 19th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2023

会议

会议	19th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2023
国家/地区	印度
市	Hyderabad
时期	19/11/23 → 22/11/23

访问文件

10.1109/APCCAS60141.2023.00058

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链接到 Scopus 的出版物

引用此

Shao, Y., Wang, C., Huang, J., Lu, W., Gu, Z., Li, L., Zhang, Y., Zhao, J., Mao, W., & Li, Y. (2023). V2Va: An Efficient Verilog-to-Verilog-A Translator for Accelerated Mixed-Signal Simulation. 在 Proceedings - 2023 19th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2023 (页码 222-226). (Proceedings - 2023 19th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2023). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APCCAS60141.2023.00058

Shao, Yicong ; Wang, Chao ; Huang, Jiajie 等. / V2Va : An Efficient Verilog-to-Verilog-A Translator for Accelerated Mixed-Signal Simulation. Proceedings - 2023 19th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2023. Institute of Electrical and Electronics Engineers Inc., 2023. 页码 222-226 (Proceedings - 2023 19th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2023).

@inproceedings{3b50ba93adaf40ebaf20a6a842bd6876,

title = "V2Va: An Efficient Verilog-to-Verilog-A Translator for Accelerated Mixed-Signal Simulation",

abstract = "This paper introduces a streamlined Verilog-to-Verilog-A (V2Va) translation tool that automates the conversion of Verilog designs into Verilog-A, enabling concurrent simulation of analog and digital circuits. Through a set of mapping rules, V2Va facilitates mixed-signal simulations in an analog environment, negating the requirement for a separate mixed-signal simulation engine and overcoming multiple types of EDA licensing obstacles. Our methodology demonstrates a notable acceleration in mixed-signal simulation, surpassing 2 ×, underscoring its significant impact and applicability in the domain of circuit design.",

keywords = "Mixed-signal Simulation, Verilog, Verilog-A, abstract syntax tree, generator, translator",

author = "Yicong Shao and Chao Wang and Jiajie Huang and Wangzilu Lu and Zhiwen Gu and Longfan Li and Yuhang Zhang and Jian Zhao and Wei Mao and Yongfu Li",

note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 19th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2023 ; Conference date: 19-11-2023 Through 22-11-2023",

year = "2023",

doi = "10.1109/APCCAS60141.2023.00058",

language = "英语",

series = "Proceedings - 2023 19th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2023",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "222--226",

booktitle = "Proceedings - 2023 19th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2023",

address = "美国",

}

Shao, Y, Wang, C, Huang, J, Lu, W, Gu, Z, Li, L, Zhang, Y, Zhao, J, Mao, W & Li, Y 2023, V2Va: An Efficient Verilog-to-Verilog-A Translator for Accelerated Mixed-Signal Simulation. 在 Proceedings - 2023 19th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2023. Proceedings - 2023 19th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2023, Institute of Electrical and Electronics Engineers Inc., 页码 222-226, 19th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2023, Hyderabad, 印度, 19/11/23. https://doi.org/10.1109/APCCAS60141.2023.00058

V2Va: An Efficient Verilog-to-Verilog-A Translator for Accelerated Mixed-Signal Simulation. / Shao, Yicong; Wang, Chao; Huang, Jiajie 等.
Proceedings - 2023 19th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2023. Institute of Electrical and Electronics Engineers Inc., 2023. 页码 222-226 (Proceedings - 2023 19th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2023).

科研成果: 书/报告/会议事项章节 › 会议稿件 › 同行评审

TY - GEN

T1 - V2Va

T2 - 19th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2023

AU - Shao, Yicong

AU - Wang, Chao

AU - Huang, Jiajie

AU - Lu, Wangzilu

AU - Gu, Zhiwen

AU - Li, Longfan

AU - Zhang, Yuhang

AU - Zhao, Jian

AU - Mao, Wei

AU - Li, Yongfu

PY - 2023

Y1 - 2023

N2 - This paper introduces a streamlined Verilog-to-Verilog-A (V2Va) translation tool that automates the conversion of Verilog designs into Verilog-A, enabling concurrent simulation of analog and digital circuits. Through a set of mapping rules, V2Va facilitates mixed-signal simulations in an analog environment, negating the requirement for a separate mixed-signal simulation engine and overcoming multiple types of EDA licensing obstacles. Our methodology demonstrates a notable acceleration in mixed-signal simulation, surpassing 2 ×, underscoring its significant impact and applicability in the domain of circuit design.

AB - This paper introduces a streamlined Verilog-to-Verilog-A (V2Va) translation tool that automates the conversion of Verilog designs into Verilog-A, enabling concurrent simulation of analog and digital circuits. Through a set of mapping rules, V2Va facilitates mixed-signal simulations in an analog environment, negating the requirement for a separate mixed-signal simulation engine and overcoming multiple types of EDA licensing obstacles. Our methodology demonstrates a notable acceleration in mixed-signal simulation, surpassing 2 ×, underscoring its significant impact and applicability in the domain of circuit design.

KW - Mixed-signal Simulation

KW - Verilog

KW - Verilog-A

KW - abstract syntax tree

KW - generator

KW - translator

UR - https://www.scopus.com/pages/publications/85192807936

U2 - 10.1109/APCCAS60141.2023.00058

DO - 10.1109/APCCAS60141.2023.00058

M3 - 会议稿件

AN - SCOPUS:85192807936

T3 - Proceedings - 2023 19th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2023

SP - 222

EP - 226

BT - Proceedings - 2023 19th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2023

PB - Institute of Electrical and Electronics Engineers Inc.

Y2 - 19 November 2023 through 22 November 2023

ER -

Shao Y, Wang C, Huang J, Lu W, Gu Z, Li L 等. V2Va: An Efficient Verilog-to-Verilog-A Translator for Accelerated Mixed-Signal Simulation. 在 Proceedings - 2023 19th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2023. Institute of Electrical and Electronics Engineers Inc. 2023. 页码 222-226. (Proceedings - 2023 19th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2023). doi: 10.1109/APCCAS60141.2023.00058

V2Va: An Efficient Verilog-to-Verilog-A Translator for Accelerated Mixed-Signal Simulation

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