The impact of negative bias temperature instability (NBTI) effect on D flip-flop

As semiconductor manufacturing has entered into the nanoscale era, performance degradation due to Negative Bias Temperature Instability (NBTI), has become one of the major threats to circuit reliability. This paper evaluates the severity of the NBTI-induced degradation in a D flip-flop based on a master-slave structure. The effectiveness of this framework is demonstrated by using a 40-nm technology model. First, the impact of the NBTI on a Positive Channel Metal Oxide Semiconductor (PMOS) device is investigated and the increase of a threshold voltage over time at different duty cycle values is presented. Using this model, the NBTI-induced degradation on the inverter and the TG are respectively discussed. Simulation results reveal that the NBTI can cause up 30% total delay both to the inverter and the TG over ten years’ operation. In particular, this work includes a simple framework integrated with the NBTI effect on D flip-flop, analyzing the impact of the degradation of propagation time and setup time under different operational conditions.