Synthesis of multi-dimensional applications in VHDL

The VHDL language is considered to be an important standard among the hardware description tools. Most of the existing loop optimization techniques that consider the parallelism inherent to multi-dimensional problems depend on loop transformations not available in the current VHDL Synthesis products. This study presents a coding technique on modeling multi-dimensional (nested) loops on VHDL, where pre-processor tools can rewrite the VHDL instructions in such a way that the optimized design can be synthesized. This new approach is expected to improve the VHDL design cycle by including multi-dimensional signal processing and other common applications in the scope of the VHDL Synthesis tools.