Software-Hardware Co-Design for Feature Extraction on Racetrack Memory-Based PIM

CNNs, which involve intensive matrix computations, often face memory bandwidth bottlenecks that PIM architectures aim to overcome. RM, with its high density, low power consumption, and excellent endurance, is particularly suited for storing matrix data in such architectures. We propose a software-level data placement strategy, tile blocking, designed to optimize the shift-based access mechanism inherent in RM. We integrate this strategy into a hardware-software co-design framework for CNN feature extraction. Our approach enhances data parallelism and significantly reduces the number of shift operations, thereby achieving energy-efficient computation on RM-based PIM systems. Experimental results demonstrate that our strategy reduced the average number of shifts by approximately 81.64%, reduced the average energy by approximately 38.68%, and reduced the average execution time by approximately 44.7%.