@inproceedings{29f111ef6b234277bf3369826165e05e,
title = "Research of segmented 8bit voltage-mode R-2R ladder DAC",
abstract = "Modeling for voltage-mode R-2R ladder digital to analog converter (DAC) is introduced in this paper. By analyzing the mismatch of resistors in ladder, the DNL and INL calculation expression are obtained. In order to achieve a higher accuracy, segmentation is used in DAC. Five different segmentation methods are compared and 3+5 segmentation structure is chosen to achieve best DNL and INL performance. For post calibration, a code-dependent current consumption expression is derived from the input impedance of R-2R ladder. A 3+5 segmented DAC based on this modeling is implemented in a standard 0.18μm CMOS process. The post simulation results show that DNL and INL are bounded at 0.30 and 0.32LSB.",
author = "Wei Xu and Runxi Zhang and Chunqi Shi",
note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; 11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015 ; Conference date: 03-11-2015 Through 06-11-2015",
year = "2016",
month = jul,
day = "21",
doi = "10.1109/ASICON.2015.7517105",
language = "英语",
series = "Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
editor = "Junyan Ren and Ting-Ao Tang and Fan Ye and Huihua Yu",
booktitle = "Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015",
address = "美国",
}