RAR: Remapping Algorithm of Racetrack Memory Based Main-Memory for Parallelism Improvement

Racetrack Memory (RTM), as a promising next-generation memory technology, offers high storage density and low access latency. It is a potential alternative to DRAM in main-memory applications. However, the data access pattern of RTM differs from traditional memory. Its 'shift before access' characteristic presents challenges for efficient memory management and rapid data access. This article proposes a novel address remapping algorithm for RTM to improve data access efficiency in these contexts. By analyzing memory access locality and computing weights based on trace patterns, our method distributes data across multiple banks to reduce access contention caused by sequential access within a single bank. In addition, we introduce a workload balancing mechanism to achieve wear leveling, which further optimizes overall parallelism and reduces performance bottlenecks in the RTM storage system. We evaluate the proposed algorithm on 15 real-world SPEC2006 benchmarks, which demonstrates that address remapping reduces the number of shifts by 10.9 % and the total bank energy by 10.1 %. Furthermore, our strategy leads to a 10.2 % reduction in the average latency of single trace. These results highlight the potential of RTM in main-memory applications where low energy consumption and high throughput are crucial. Additionally, they illustrate the effectiveness of our approach in optimizing RTM performance for real-world, latency-sensitive workloads.