摘要
At the system level design of a real-time embedded system, a major issue is to identify from alternative architectures the best one which satisfies the timing constraints. This issue leads to the need of a metric that is capable of evaluating the overall system timing performance. Some of the previous work in the related areas focus on predicting the system's timing performance based on a fixed computation time model. These approaches are often too pessimistic. Those that do consider varying computation times for each task are only concerned with the timing behavior of each individual task. Such predictions may not properly capture the timing behavior of the entire system. In this paper, we introduce a metric that reflects the overall timing behavior of RTES. Applying this metric allows a comprehensive comparison of alternative system level designs.
| 源语言 | 英语 |
|---|---|
| 页 | 90-94 |
| 页数 | 5 |
| 出版状态 | 已出版 - 1999 |
| 已对外发布 | 是 |
| 活动 | Proceedings of the 1999 7th International Conference on Hardware/Software Codesign (CODES'99) - Rome, Italy 期限: 3 5月 1999 → 5 5月 1999 |
会议
| 会议 | Proceedings of the 1999 7th International Conference on Hardware/Software Codesign (CODES'99) |
|---|---|
| 市 | Rome, Italy |
| 时期 | 3/05/99 → 5/05/99 |
指纹
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