@inproceedings{7ccca13e88a142be96de83b9cf0d0a4a,
title = "Performance Trade-offs in Complementary FET (CFET) Device Architectures for 3nm-node and beyond",
abstract = "A comparative analysis of DC/AC performance of complementary FET (CFET) is presented by 3D TCAD simulation for 3nm-node and beyond. Three types of device architectures with different structure parameters are investigated and compared on some critical electrical characteristics. Through adjusting the fin height and width, the source/drain-extension-to-gate underlap length and the n-/p-FET separator thickness and material, the tradeoff between DC and AC performance is shown to give an optimized CFET device architecture.",
keywords = "CFET, TCAD, gate-all-around (GAA)",
author = "Xiaoqiao Yang and Yabin Sun and Ziyu Liu and Yanling Shi and Xiaojin Li",
note = "Publisher Copyright: {\textcopyright} 2021 IEEE.; 5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021 ; Conference date: 08-04-2021 Through 11-04-2021",
year = "2021",
month = apr,
day = "8",
doi = "10.1109/EDTM50988.2021.9420820",
language = "英语",
series = "2021 5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2021 5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021",
address = "美国",
}