Performance optimization of multiple memory architectures for DSP

Multiple memory module architecture enjoys higher memory access bandwidth and thus higher performance. Two key problems in gaining high performance in this kind of architecture are variable partitioning and scheduling. However, there's little research work that has been done on these problems. In this paper, we present a new graph model for tackling the variable partitioning problem, namely, Variable Independence Graph (VIG), which provides more precise information for variable partitioning compared to the previous graph models. We also present a scheduling algorithm that takes advantages of multiple memory modules, Rotation Scheduling with Variable Re-partition (RSVR). It's a new scheduling technique based on retiming and software pipelining. It may re-partition the variables if necessary during the scheduling process. The experiment results show that the average improvement on schedule length by using the algorithm is 44.8%. Another major contribution of this paper is that we invent an algorithm for design space exploration on multiple memory architecture. It produces more feasible solutions on a set of schedule length requirement. And our solution have less functional units that Interference Graph model.