Modeling and simulation for NBTI-considered path delay prediction in logical circuit

NBTI (Negative Bias Temperature Instability) is a major concern in long-time circuit performance. In this paper, NBTI degradation models of basic logic gates have been developed based on the conventional reaction-diffusion (R-D) model which is used to predict the threshold voltage shift (ΔV _TH) of p-type MOSFET. Besides load capacitance (C_L), input slew rate (t_i) and supply voltage (V_DD), ΔV _TH versus gate delay degradation of NAND, INV, and NOR have been evaluated and approximated by second-order polynomials. Furthermore, a method to calculate the degradation of circuit speed over a long period of time given input switching rate, duty factor and power supply, is built up. Finally, the effectiveness of the proposed has been demonstrated with the ISCAS'85 benchmark circuit.