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Loop scheduling optimization for chip-multiprocessors with non-volatile main memory

  • Hunan University
  • University of Texas at Dallas
  • Chongqing University

科研成果: 书/报告/会议事项章节会议稿件同行评审

摘要

Non-Volatile Memories (NVMs) have many advantages over traditional DRAM. It is desirable to apply NVM as main memory in embedded Chip Multi-Processor (CMP) systems. However, NVMs have drawbacks that need to be overcome. That is, a write to the NVMs is expensive. Loops are the most critical and time-consuming part in digital signal processing (DSP) applications. However, loops are difficult to parallelize on multi-processor systems due to the inter-iteration dependencies. This paper targets on embedded CMP systems and proposes techniques to improve loop parallelism while considering reducing the write activities to the NVMs when they are used as main memory. The experimental results show that the proposed algorithm can reduce the number of write activities on NVM by 21.1% on average. In other words, the average lifetime of NVM can be extended to at least 2 times longer than before and the total schedule length is reduced by 19.6% on average.

源语言英语
主期刊名2012 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2012 - Proceedings
1553-1556
页数4
DOI
出版状态已出版 - 2012
已对外发布
活动2012 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2012 - Kyoto, 日本
期限: 25 3月 201230 3月 2012

出版系列

姓名ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
ISSN(印刷版)1520-6149

会议

会议2012 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2012
国家/地区日本
Kyoto
时期25/03/1230/03/12

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