Iterational retiming: Maximize iteration-level parallelism for nested loops

Nested loops are the most critical sections in many scientific and Digital Signal Processing (DSP) applications. It is important to study effective and efficient transformation techniques to increase parallelism for nested loops. In this paper, we propose a novel technique, iterational retiming, that can satisfy any given timing constraint by achieving full parallelism for iterations in a partition. Theorems and efficient algorithms are proposed for iterational retiming. The experimental results show that iterational retiming is a promising technique for parallel embedded systems. It can achieve 87% improvement over software pipelining and 88% improvement over loop unfolding on average.