@inproceedings{d6bd038178a441f99c7334e111a5a7ed,
title = "Influence of Gate-Drain Underlap Length on Germanium Gate-All-Around Tunneling Field-Effect-Transistors",
abstract = "In this paper, the influence of gate-drain underlap length (Lun) of germanium gate-all-around tunneling field-effect-transistors (Ge-GAA- TFETs) is investigated. Based on the TCAD simulation, the I- V and C- V characteristics of GAA- TFETs with different Lunare obtained, and the results show that ambipolar current (Iamp) and Cgd considerably decrease with the increase in Lun, whereas Cgs is independent on Lun. Moreover, the method of device circuit co-design is used to evaluate the impact of Lunon logic performance including propagation delay (tpd) and energy-delay-product (EDP). Compared with no underlap structure, the tpd reduction of 40\% @VDD= 0.2 V is achieved in both inverter and two-input NAND with 10 nm underlap structure. The EDP reduction up to 67\% and 66\% at VDD= 0.2 V are obtained in the inverter and two-input NAND, respectively. Therefore, we can conclude that the longer Lunbenefits in mitigating both tpd and EDP.",
author = "Wei, \{Kai Xiao\} and Li, \{Xiao Jin\} and Sun, \{Ya Bin\} and Shi, \{Yan Ling\}",
note = "Publisher Copyright: {\textcopyright} 2020 IEEE.; 15th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020 ; Conference date: 03-11-2020 Through 06-11-2020",
year = "2020",
month = nov,
day = "3",
doi = "10.1109/ICSICT49897.2020.9278269",
language = "英语",
series = "2020 IEEE 15th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020 - Proceedings",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
editor = "Shaofeng Yu and Xiaona Zhu and Ting-Ao Tang",
booktitle = "2020 IEEE 15th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020 - Proceedings",
address = "美国",
}