@inproceedings{92735915f02944678c9a20e7dc0f2f5c,
title = "Gate-to-source/drain fringing capacitance model with process variation of MOSFET in 40nm generation",
abstract = "In this paper, a semi-analytical model for the gate-to-source/drain fringing capacitance (Cf) of MOSFET including process variations is presented. Cf is defined as a layout-dependent parasitic capacitance separated from gate-to-contact capacitance (Cco), and is composed of several dual-k perpendicular-plate capacitances. Layout-dependent coefficients such as gate to contact space (CPS) and contact to contact space (CCS) are found to significantly influence Cf. According to the silicon data, Cf model is optimized including the process variation. The errors between silicon data and simulation are under 15\%. The proposed model can improve the precision for digital and RF circuit simulation in sub-nanometer technology generation.",
author = "Jiaqi Ren and Lijie Sun and Fanglin Zheng and Yabin Sun and Xiaojin Li and Yanling Shi",
note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 ; Conference date: 25-10-2016 Through 28-10-2016",
year = "2016",
doi = "10.1109/ICSICT.2016.7999048",
language = "英语",
series = "2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "808--810",
editor = "Yu-Long Jiang and Ting-Ao Tang and Ru Huang",
booktitle = "2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings",
address = "美国",
}