FCP-LLM: Functional Coverpoint Plan Generation Using LLM in Early Design Verification Stage

During the design process of digital integrated circuits, high-quality coverpoint plan plays a crucial role, as it guides the verification process. This challenging task is accomplished by experienced engineers who consume a massive amount of time to extract critical information from design specifications. In this work, we present the FCP-LLM framework that is designed to understand both design specifications and Hardware Description Language (HDL) code to focus on extracting critical edges of designs' ports. It consists of three main components: CP-Generator for creating coverpoint plans, CP-Reviewer for refining the plans, and SV-Coder for generating SystemVerilog code. It has been evaluated with a series of benchmark circuits, comprising 74X-Series circuits and custom digital designs. Our experimental results show that FCP-LLM outperforms the baseline work with an average improvement of exceeding 300%, demonstrating a better balance between effectiveness and redundancy in coverpoint plan generation.