Erratum: Correction: 12-state multi-level cell storage implemented in a 128 Mb phase change memory chip (Nanoscale (2021) 13 23 (10455-10461))

Zhitang Song; Daolin Cai; Yan Cheng; Lei Wang; Shilong Lv; Tianjiao Xin; Gaoming Feng

doi:10.1039/d1nr90100a

Erratum: Correction: 12-state multi-level cell storage implemented in a 128 Mb phase change memory chip (Nanoscale (2021) 13 23 (10455-10461))

Zhitang Song
, Daolin Cai
, Yan Cheng
, Lei Wang
, Shilong Lv
, Tianjiao Xin
, Gaoming Feng

物理与电子科学学院

CAS - Shanghai Institute of Microsystem and Information Technology
Semiconductor Manufacturing International Corporation Shanghai

科研成果: 期刊稿件 › 评论/辩论

摘要

Correction for '12-state multi-level cell storage implemented in a 128 Mb phase change memory chip' by Zhitang Song et al., Nanoscale, 2021, DOI: 10.1039/d1nr00100k.

源语言	英语
页（从-至）	10608-10609
页数	2
期刊	Nanoscale
卷	13
期	23
DOI	https://doi.org/10.1039/d1nr90100a
出版状态	已出版 - 17 6月 2021

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10.1039/d1nr90100a

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title = "Erratum: Correction: 12-state multi-level cell storage implemented in a 128 Mb phase change memory chip (Nanoscale (2021) 13 23 (10455-10461))",

abstract = "Correction for '12-state multi-level cell storage implemented in a 128 Mb phase change memory chip' by Zhitang Song et al., Nanoscale, 2021, DOI: 10.1039/d1nr00100k.",

author = "Zhitang Song and Daolin Cai and Yan Cheng and Lei Wang and Shilong Lv and Tianjiao Xin and Gaoming Feng",

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AU - Song, Zhitang

AU - Cai, Daolin

AU - Cheng, Yan

AU - Wang, Lei

AU - Lv, Shilong

AU - Xin, Tianjiao

AU - Feng, Gaoming

PY - 2021/6/17

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M3 - 评论/辩论

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Erratum: Correction: 12-state multi-level cell storage implemented in a 128 Mb phase change memory chip (Nanoscale (2021) 13 23 (10455-10461))

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