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DPP-MP: An Area-Efficient Digital Predistortion Model for Quadrature Digital Transmitters

  • Yuan Xu
  • , Kangjie Zhao
  • , Wangdong Xie
  • , Guozhen Wu
  • , Leilei Huang*
  • , Chunqi Shi*
  • , Jinghong Chen
  • , Runxi Zhang
  • *此作品的通讯作者
  • East China Normal University
  • University of Houston

科研成果: 书/报告/会议事项章节 › 会议稿件 › 同行评审

摘要

Although quadrature digital transmitters (DTXs) are particularly useful in wideband scenarios, the interaction between I and Q paths would lead to a non-negligible distortion. Unfortunately, traditional DPD models have not performed well in solving this kind of distortion. For example, memory polynomial (MP) model uses signal amplitude as the fundamental term which is not accurate enough to solve this issue, while 2-D lookup table (2D-LUT) model requires a large number of entries which leads to significant hardware resource consumption. In view of this, we propose an area-efficient dual-path piecewise memory-polynomial (DPP-MP) model, which improves model accuracy while reducing hardware resource consumption. To further reduce the area cost, the model is pruned to 8 terms only and 4 of them are reused. To reduce the logic delay, a new squared multiplier is proposed to replace the default one, which reduces delay by 13.51% and power consumption by 2.56%. This model achieves 36.86% and 66.98% area optimization compared to MP and 2D-LUT, respectively. When applied to a 9-bit quadrature DTX with a 40 MHz 256-QAM signal, this model improves the error vector magnitude (EVM) from -16.38 dB to -35.89 dB with a target average power (Pavg) of 21.07 dBm.

源语言英语
主期刊名ISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings
出版商Institute of Electrical and Electronics Engineers Inc.
ISBN(电子版)9798350356830
DOI
出版状态已出版 - 2025
活动2025 IEEE International Symposium on Circuits and Systems, ISCAS 2025 - London, 英国
期限: 25 5月 2025 → 28 5月 2025

丛书

姓名Proceedings - IEEE International Symposium on Circuits and Systems
ISSN(印刷版)0271-4310

会议

会议2025 IEEE International Symposium on Circuits and Systems, ISCAS 2025
国家/地区英国
市London
时期25/05/25 → 28/05/25

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