Design Technology Co-Optimization for 3 nm Gate-All-Around Nanosheet FETs

Meng Wang; Yabin Sun; Xiaojin Li; Yanling Shi; Shaojian Hu; Enming Shang; Shoumian Chen

doi:10.1109/ICSICT49897.2020.9278197

Design Technology Co-Optimization for 3 nm Gate-All-Around Nanosheet FETs

Meng Wang
, Yabin Sun^*
, Xiaojin Li
, Yanling Shi
, Shaojian Hu
, Enming Shang
, Shoumian Chen

^*此作品的通讯作者

通信与电子工程学院

East China Normal University
Integrated Circuit Research and Development Center

科研成果: 书/报告/会议事项章节 › 会议稿件 › 同行评审

12 引用（Scopus）

摘要

In this work, an improved TCAD based Design Technology Co-Optimization (DTCO) is proposed for gate-All-Around (GAA) Nanosheet FET (NSFET) at 3 nm technology node. Based on conventional DTCO, only an additional procedure is introduced to extract the SPICE model, while the huge computational expense in the TCAD simulation is saved. Compared to the 5 nm technology node, the performance of ring oscillator (RO) in the optimized 3 nm technology node increases by 30%, while the power decreases by 56%. Besides, dual-k spacer design for NSFETs at the device and circuit levels are also investigated.

源语言	英语
主期刊名	2020 IEEE 15th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020 - Proceedings
编辑	Shaofeng Yu, Xiaona Zhu, Ting-Ao Tang
出版商	Institute of Electrical and Electronics Engineers Inc.
ISBN（电子版）	9781728162355
DOI	https://doi.org/10.1109/ICSICT49897.2020.9278197
出版状态	已出版 - 3 11月 2020
活动	15th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020 - Virtual, Kunming, 中国期限: 3 11月 2020 → 6 11月 2020

出版系列

姓名	2020 IEEE 15th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020 - Proceedings

会议

会议	15th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020
国家/地区	中国
市	Virtual, Kunming
时期	3/11/20 → 6/11/20

访问文件

10.1109/ICSICT49897.2020.9278197

其它文件与链接

链接到 Scopus 的出版物

引用此

Wang, M., Sun, Y., Li, X., Shi, Y., Hu, S., Shang, E., & Chen, S. (2020). Design Technology Co-Optimization for 3 nm Gate-All-Around Nanosheet FETs. 在 S. Yu, X. Zhu, & T.-A. Tang (编辑), 2020 IEEE 15th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020 - Proceedings 文章 9278197 (2020 IEEE 15th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICSICT49897.2020.9278197

Wang, Meng ; Sun, Yabin ; Li, Xiaojin 等. / Design Technology Co-Optimization for 3 nm Gate-All-Around Nanosheet FETs. 2020 IEEE 15th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020 - Proceedings. 编辑 / Shaofeng Yu ; Xiaona Zhu ; Ting-Ao Tang. Institute of Electrical and Electronics Engineers Inc., 2020. (2020 IEEE 15th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020 - Proceedings).

@inproceedings{b35de37d72b24b8cae7107bc372b3471,

title = "Design Technology Co-Optimization for 3 nm Gate-All-Around Nanosheet FETs",

abstract = "In this work, an improved TCAD based Design Technology Co-Optimization (DTCO) is proposed for gate-All-Around (GAA) Nanosheet FET (NSFET) at 3 nm technology node. Based on conventional DTCO, only an additional procedure is introduced to extract the SPICE model, while the huge computational expense in the TCAD simulation is saved. Compared to the 5 nm technology node, the performance of ring oscillator (RO) in the optimized 3 nm technology node increases by 30\%, while the power decreases by 56\%. Besides, dual-k spacer design for NSFETs at the device and circuit levels are also investigated.",

author = "Meng Wang and Yabin Sun and Xiaojin Li and Yanling Shi and Shaojian Hu and Enming Shang and Shoumian Chen",

note = "Publisher Copyright: {\textcopyright} 2020 IEEE.; 15th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020 ; Conference date: 03-11-2020 Through 06-11-2020",

year = "2020",

month = nov,

day = "3",

doi = "10.1109/ICSICT49897.2020.9278197",

language = "英语",

series = "2020 IEEE 15th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020 - Proceedings",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

editor = "Shaofeng Yu and Xiaona Zhu and Ting-Ao Tang",

booktitle = "2020 IEEE 15th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020 - Proceedings",

address = "美国",

}

Wang, M, Sun, Y , Li, X, Shi, Y, Hu, S, Shang, E & Chen, S 2020, Design Technology Co-Optimization for 3 nm Gate-All-Around Nanosheet FETs. 在 S Yu, X Zhu & T-A Tang (编辑), 2020 IEEE 15th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020 - Proceedings., 9278197, 2020 IEEE 15th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020 - Proceedings, Institute of Electrical and Electronics Engineers Inc., 15th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020, Virtual, Kunming, 中国, 3/11/20. https://doi.org/10.1109/ICSICT49897.2020.9278197

Design Technology Co-Optimization for 3 nm Gate-All-Around Nanosheet FETs. / Wang, Meng; Sun, Yabin ; Li, Xiaojin 等.
2020 IEEE 15th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020 - Proceedings. 编辑 / Shaofeng Yu; Xiaona Zhu; Ting-Ao Tang. Institute of Electrical and Electronics Engineers Inc., 2020. 9278197 (2020 IEEE 15th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020 - Proceedings).

科研成果: 书/报告/会议事项章节 › 会议稿件 › 同行评审

TY - GEN

T1 - Design Technology Co-Optimization for 3 nm Gate-All-Around Nanosheet FETs

AU - Wang, Meng

AU - Sun, Yabin

AU - Li, Xiaojin

AU - Shi, Yanling

AU - Hu, Shaojian

AU - Shang, Enming

AU - Chen, Shoumian

PY - 2020/11/3

Y1 - 2020/11/3

N2 - In this work, an improved TCAD based Design Technology Co-Optimization (DTCO) is proposed for gate-All-Around (GAA) Nanosheet FET (NSFET) at 3 nm technology node. Based on conventional DTCO, only an additional procedure is introduced to extract the SPICE model, while the huge computational expense in the TCAD simulation is saved. Compared to the 5 nm technology node, the performance of ring oscillator (RO) in the optimized 3 nm technology node increases by 30%, while the power decreases by 56%. Besides, dual-k spacer design for NSFETs at the device and circuit levels are also investigated.

AB - In this work, an improved TCAD based Design Technology Co-Optimization (DTCO) is proposed for gate-All-Around (GAA) Nanosheet FET (NSFET) at 3 nm technology node. Based on conventional DTCO, only an additional procedure is introduced to extract the SPICE model, while the huge computational expense in the TCAD simulation is saved. Compared to the 5 nm technology node, the performance of ring oscillator (RO) in the optimized 3 nm technology node increases by 30%, while the power decreases by 56%. Besides, dual-k spacer design for NSFETs at the device and circuit levels are also investigated.

UR - https://www.scopus.com/pages/publications/85099254709

U2 - 10.1109/ICSICT49897.2020.9278197

DO - 10.1109/ICSICT49897.2020.9278197

M3 - 会议稿件

AN - SCOPUS:85099254709

T3 - 2020 IEEE 15th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020 - Proceedings

BT - 2020 IEEE 15th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020 - Proceedings

A2 - Yu, Shaofeng

A2 - Zhu, Xiaona

A2 - Tang, Ting-Ao

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 15th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020

Y2 - 3 November 2020 through 6 November 2020

ER -

Wang M, Sun Y , Li X, Shi Y, Hu S, Shang E 等. Design Technology Co-Optimization for 3 nm Gate-All-Around Nanosheet FETs. 在 Yu S, Zhu X, Tang TA, 编辑, 2020 IEEE 15th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2020. 9278197. (2020 IEEE 15th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020 - Proceedings). doi: 10.1109/ICSICT49897.2020.9278197

Design Technology Co-Optimization for 3 nm Gate-All-Around Nanosheet FETs

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