Design of Digital Baseband Architecture for Low-Power Passive UHF RFID Tag

With the development of radio frequency identification technology, UHF RFID technology has become a major research hotspot. Since the power supply energy of passive tags comes from the coupling of electromagnetic fields in space, the design of low power consumption has become a crucial factor affecting the performance of UHF RFID tags. This paper proposed a low-power passive UHF RFID tag chip digital baseband architecture based on ISO/IEC 18000-6C standard. The clock resources of each module are reasonably allocated through low-power design methods such as clock frequency division, gated clock, command execution clock design, and adopting asynchronous counter. After function simulation and power consumption simulation, the whole digital baseband can realize 13 commands with power consumption of only 4.3 μ ~W, which meets the daily use and ultra-low power consumption requirements of passive RFID chips.