Design of All-Digital Two Phase Ping-Pong Switched Capacitor Voltage Doubler Power Converter

Zhiwen Gu; Feng Yang; Yuhang Zhang; Yanhan Zeng; Zhihong Luo; Yuan Du; Li Du; Yongfu Li

doi:10.1109/TCSII.2023.3287794

Design of All-Digital Two Phase Ping-Pong Switched Capacitor Voltage Doubler Power Converter

Zhiwen Gu
, Feng Yang
, Yuhang Zhang
, Yanhan Zeng
, Zhihong Luo
, Yuan Du
, Li Du
, Yongfu Li^*

^*此作品的通讯作者

Shanghai Jiao Tong University
Guangzhou University
Primarius Technologies
Nanjing University

科研成果: 期刊稿件 › 文章 › 同行评审

2 引用（Scopus）

摘要

This brief presents an all-digital two-phase Ping Pong voltage doubler with reduced reversion loss by introducing additional switches in the loss path. It is implemented using inverter logic circuits with MOM capacitors stacked on top, which is compatible with digital design flow. With varying clock conditions, the proposed circuit reduces voltage ripples down to 239.9 mV with a voltage drop of less than 20.2 mV (measured). The traditional circuit has a voltage ripple of up to 999 mV with a 171.3 mV voltage drop (simulated). The proposed circuit achieves a peak efficiency of 91.68%.

源语言	英语
页（从-至）	3807-3811
页数	5
期刊	IEEE Transactions on Circuits and Systems II: Express Briefs
卷	70
期	10
DOI	https://doi.org/10.1109/TCSII.2023.3287794
出版状态	已出版 - 1 10月 2023
已对外发布	是

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10.1109/TCSII.2023.3287794

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title = "Design of All-Digital Two Phase Ping-Pong Switched Capacitor Voltage Doubler Power Converter",

abstract = "This brief presents an all-digital two-phase Ping Pong voltage doubler with reduced reversion loss by introducing additional switches in the loss path. It is implemented using inverter logic circuits with MOM capacitors stacked on top, which is compatible with digital design flow. With varying clock conditions, the proposed circuit reduces voltage ripples down to 239.9 mV with a voltage drop of less than 20.2 mV (measured). The traditional circuit has a voltage ripple of up to 999 mV with a 171.3 mV voltage drop (simulated). The proposed circuit achieves a peak efficiency of 91.68\%.",

keywords = "Charge pumps, dynamic voltage scaling, reversion power loss, switched capacitor (SC) power converter",

author = "Zhiwen Gu and Feng Yang and Yuhang Zhang and Yanhan Zeng and Zhihong Luo and Yuan Du and Li Du and Yongfu Li",

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doi = "10.1109/TCSII.2023.3287794",

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T1 - Design of All-Digital Two Phase Ping-Pong Switched Capacitor Voltage Doubler Power Converter

AU - Gu, Zhiwen

AU - Yang, Feng

AU - Zhang, Yuhang

AU - Zeng, Yanhan

AU - Luo, Zhihong

AU - Du, Yuan

AU - Du, Li

AU - Li, Yongfu

PY - 2023/10/1

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N2 - This brief presents an all-digital two-phase Ping Pong voltage doubler with reduced reversion loss by introducing additional switches in the loss path. It is implemented using inverter logic circuits with MOM capacitors stacked on top, which is compatible with digital design flow. With varying clock conditions, the proposed circuit reduces voltage ripples down to 239.9 mV with a voltage drop of less than 20.2 mV (measured). The traditional circuit has a voltage ripple of up to 999 mV with a 171.3 mV voltage drop (simulated). The proposed circuit achieves a peak efficiency of 91.68%.

AB - This brief presents an all-digital two-phase Ping Pong voltage doubler with reduced reversion loss by introducing additional switches in the loss path. It is implemented using inverter logic circuits with MOM capacitors stacked on top, which is compatible with digital design flow. With varying clock conditions, the proposed circuit reduces voltage ripples down to 239.9 mV with a voltage drop of less than 20.2 mV (measured). The traditional circuit has a voltage ripple of up to 999 mV with a 171.3 mV voltage drop (simulated). The proposed circuit achieves a peak efficiency of 91.68%.

KW - Charge pumps

KW - dynamic voltage scaling

KW - reversion power loss

KW - switched capacitor (SC) power converter

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JO - IEEE Transactions on Circuits and Systems II: Express Briefs

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Design of All-Digital Two Phase Ping-Pong Switched Capacitor Voltage Doubler Power Converter

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