Compiler-assisted refresh minimization for volatile STT-RAM cache

Qingan Li; Jianhua Li; Liang Shi; Chun Jason Xue; Yiran Chen; Yanxiang He

doi:10.1109/ASPDAC.2013.6509608

Compiler-assisted refresh minimization for volatile STT-RAM cache

Qingan Li
, Jianhua Li
, Liang Shi
, Chun Jason Xue
, Yiran Chen
, Yanxiang He

City University of Hong Kong
University of Pittsburgh
Wuhan University

科研成果: 书/报告/会议事项章节 › 会议稿件 › 同行评审

18 引用（Scopus）

摘要

Spin-Transfer Torque RAM (STT-RAM) has been proposed to build on-chip caches because of its attractive features: high storage density and negligible leakage power. Recently, researchers propose to improve the write performance of STT-RAM by relaxing its non-volatility property. To avoid data loss resulting from volatility, refresh schemes are proposed. However, refresh operations consume additional energy. In this paper, we propose to reduce the number of refresh operations through re-arranging program data layout at compilation time. An N-refresh scheme is also proposed. Experimental results show that, on average, the proposedmethods can reduce the number of refresh operations by 73.3%, and reduce the dynamic energy consumption by 27.6%.

源语言	英语
主期刊名	2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013
页	273-278
页数	6
DOI	https://doi.org/10.1109/ASPDAC.2013.6509608
出版状态	已出版 - 2013
已对外发布	是
活动	2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013 - Yokohama, 日本期限: 22 1月 2013 → 25 1月 2013

出版系列

姓名	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

会议

会议	2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013
国家/地区	日本
市	Yokohama
时期	22/01/13 → 25/01/13

联合国可持续发展目标

此成果有助于实现下列可持续发展目标：

可持续发展目标 7 经济适用的清洁能源

访问文件

10.1109/ASPDAC.2013.6509608

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引用此

Li, Q., Li, J., Shi, L., Xue, C. J., Chen, Y., & He, Y. (2013). Compiler-assisted refresh minimization for volatile STT-RAM cache. 在 2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013 (页码 273-278). 文章 6509608 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1109/ASPDAC.2013.6509608

@inproceedings{06d17f622bc3449d8ed381be3dffa3b0,

title = "Compiler-assisted refresh minimization for volatile STT-RAM cache",

abstract = "Spin-Transfer Torque RAM (STT-RAM) has been proposed to build on-chip caches because of its attractive features: high storage density and negligible leakage power. Recently, researchers propose to improve the write performance of STT-RAM by relaxing its non-volatility property. To avoid data loss resulting from volatility, refresh schemes are proposed. However, refresh operations consume additional energy. In this paper, we propose to reduce the number of refresh operations through re-arranging program data layout at compilation time. An N-refresh scheme is also proposed. Experimental results show that, on average, the proposedmethods can reduce the number of refresh operations by 73.3\%, and reduce the dynamic energy consumption by 27.6\%.",

author = "Qingan Li and Jianhua Li and Liang Shi and Xue, \{Chun Jason\} and Yiran Chen and Yanxiang He",

year = "2013",

doi = "10.1109/ASPDAC.2013.6509608",

language = "英语",

isbn = "9781467330299",

series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

pages = "273--278",

booktitle = "2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013",

note = "2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013 ; Conference date: 22-01-2013 Through 25-01-2013",

}

Li, Q, Li, J, Shi, L, Xue, CJ, Chen, Y & He, Y 2013, Compiler-assisted refresh minimization for volatile STT-RAM cache. 在 2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013., 6509608, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 页码 273-278, 2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013, Yokohama, 日本, 22/01/13. https://doi.org/10.1109/ASPDAC.2013.6509608

Compiler-assisted refresh minimization for volatile STT-RAM cache. / Li, Qingan; Li, Jianhua; Shi, Liang 等.
2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013. 2013. 页码 273-278 6509608 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

科研成果: 书/报告/会议事项章节 › 会议稿件 › 同行评审

TY - GEN

T1 - Compiler-assisted refresh minimization for volatile STT-RAM cache

AU - Li, Qingan

AU - Li, Jianhua

AU - Shi, Liang

AU - Xue, Chun Jason

AU - Chen, Yiran

AU - He, Yanxiang

PY - 2013

Y1 - 2013

N2 - Spin-Transfer Torque RAM (STT-RAM) has been proposed to build on-chip caches because of its attractive features: high storage density and negligible leakage power. Recently, researchers propose to improve the write performance of STT-RAM by relaxing its non-volatility property. To avoid data loss resulting from volatility, refresh schemes are proposed. However, refresh operations consume additional energy. In this paper, we propose to reduce the number of refresh operations through re-arranging program data layout at compilation time. An N-refresh scheme is also proposed. Experimental results show that, on average, the proposedmethods can reduce the number of refresh operations by 73.3%, and reduce the dynamic energy consumption by 27.6%.

AB - Spin-Transfer Torque RAM (STT-RAM) has been proposed to build on-chip caches because of its attractive features: high storage density and negligible leakage power. Recently, researchers propose to improve the write performance of STT-RAM by relaxing its non-volatility property. To avoid data loss resulting from volatility, refresh schemes are proposed. However, refresh operations consume additional energy. In this paper, we propose to reduce the number of refresh operations through re-arranging program data layout at compilation time. An N-refresh scheme is also proposed. Experimental results show that, on average, the proposedmethods can reduce the number of refresh operations by 73.3%, and reduce the dynamic energy consumption by 27.6%.

UR - https://www.scopus.com/pages/publications/84877725977

U2 - 10.1109/ASPDAC.2013.6509608

DO - 10.1109/ASPDAC.2013.6509608

M3 - 会议稿件

AN - SCOPUS:84877725977

SN - 9781467330299

T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

SP - 273

EP - 278

BT - 2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013

T2 - 2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013

Y2 - 22 January 2013 through 25 January 2013

ER -

Compiler-assisted refresh minimization for volatile STT-RAM cache

摘要

出版系列

会议

联合国可持续发展目标

访问文件

其它文件与链接

指纹

引用此