Bus minimization and scheduling of multi-chip systems

Michael Sheliga; Edwin Hsing Mean Sha

Bus minimization and scheduling of multi-chip systems

Michael Sheliga^*
, Edwin Hsing Mean Sha

^*此作品的通讯作者

University of Notre Dame

科研成果: 期刊稿件 › 会议文章 › 同行评审

5 引用（Scopus）

摘要

This paper considers several different algorithms that reduce the required number of buses for multi-chip module design. An efficient polynomial time algorithm that calculates the minimum number of buses needed given a particular schedule is presented. We also present three algorithms that minimize the number of buses during scheduling. Experimental results are shown that illustrate the efficiency of the algorithms.

源语言	英语
页（从-至）	40-45
页数	6
期刊	Proceedings of the IEEE Great Lakes Symposium on VLSI
出版状态	已出版 - 1995
已对外发布	是
活动	Proceedings of the 5th Great Lakes Symposium on VLSI - Buffalo, NY, USA 期限: 16 3月 1995 → 18 3月 1995

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引用此

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title = "Bus minimization and scheduling of multi-chip systems",

abstract = "This paper considers several different algorithms that reduce the required number of buses for multi-chip module design. An efficient polynomial time algorithm that calculates the minimum number of buses needed given a particular schedule is presented. We also present three algorithms that minimize the number of buses during scheduling. Experimental results are shown that illustrate the efficiency of the algorithms.",

author = "Michael Sheliga and Sha, \{Edwin Hsing Mean\}",

year = "1995",

language = "英语",

pages = "40--45",

journal = "Proceedings of the IEEE Great Lakes Symposium on VLSI",

issn = "1066-1395",

publisher = "IEEE Computer Society",

note = "Proceedings of the 5th Great Lakes Symposium on VLSI ; Conference date: 16-03-1995 Through 18-03-1995",

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AU - Sheliga, Michael

AU - Sha, Edwin Hsing Mean

PY - 1995

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N2 - This paper considers several different algorithms that reduce the required number of buses for multi-chip module design. An efficient polynomial time algorithm that calculates the minimum number of buses needed given a particular schedule is presented. We also present three algorithms that minimize the number of buses during scheduling. Experimental results are shown that illustrate the efficiency of the algorithms.

AB - This paper considers several different algorithms that reduce the required number of buses for multi-chip module design. An efficient polynomial time algorithm that calculates the minimum number of buses needed given a particular schedule is presented. We also present three algorithms that minimize the number of buses during scheduling. Experimental results are shown that illustrate the efficiency of the algorithms.

UR - https://www.scopus.com/pages/publications/0029213242

M3 - 会议文章

AN - SCOPUS:0029213242

SN - 1066-1395

SP - 40

EP - 45

JO - Proceedings of the IEEE Great Lakes Symposium on VLSI

JF - Proceedings of the IEEE Great Lakes Symposium on VLSI

T2 - Proceedings of the 5th Great Lakes Symposium on VLSI

Y2 - 16 March 1995 through 18 March 1995

ER -

Bus minimization and scheduling of multi-chip systems

摘要

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引用此