Analysis and modeling of the pads for RF CMOS based on EM simulation

The modeling of the test structure of an RF MOSFET, up to 40 GHz, is presented. The size of the pads and the width of the interconnection lines of the test structures are analyzed and optimized based on accurate electromagnetic (EM) simulation in order to reduce the impact of the parasitics of the pad and interconnection lines. A 0.13 μm RF CMOS technology with eight levels of metallic layer is used to implement the test structures, which are designed according to the optimization results. Good agreement between the measured and simulated results has been demonstrated.