An Ultra-Low-Power, High-Output-Power and High-Sensitivity Bioelectronic Transceiver

This paper presents an ultra-low-power, high-output-power, and high-sensitivity transceiver for implantable bioelectronic systems in a 40-nm CMOS technology. The design targets stringent power constraints by employing a wake-up scheme. The transceiver introduces a transmitter architecture based on a cascaded injection-locked ring oscillator (ILRO) and edge combiner (EC), alongside a receiver utilizing an envelope-detection demodulation technique for power reduction. The switched-capacitor power amplifier (SCPA) enables high output power through its high-efficiency characteristic, while a high-gain low-noise amplifier (LNA) ensures high-sensitivity reception. Compared with prior works, this transceiver achieves simultaneous high output power and high sensitivity within an ultra-low-power architecture, making it ideal for implantable bioelectronic applications. The proposed techniques reduce sleep-mode power consumption to 40 nW. The transmitter delivers 2.37-dBm output power with 8.2-mW consumption, and the receiver attains -64-dBm sensitivity with 200-μW consumption over a 10-meter wireless range.