An optimized sigma-delta fractional-N frequency synthesizer for monolithic CMOS UHF RFID reader

A novel 3rd-order 3-bit single-loop sigma-delta fractional-N frequency synthesizer optimized for monolithic UHF RFID reader is fabricated in 0.18 μm CMOS technology. The phase noise requirements are recapitulated based on the proposed zero-IF architecture and EPCglobal C1G2 and ETSI RFID protocols. The measurement results show that the frequency synthesizer achieves noise suppression for additional zero configuration in noise transfer function of modulator. The measured phase noise is approximately-103 and-132 dBc/Hz at 200 kHz and 1 MHz offsets from 900 MHz center frequency while drawing 9.6 mA from 1.8 V power supply.