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An optimized ΔΣ fractional-N frequency synthesizer for CMOS UHF RFID reader

  • East China Normal University

科研成果: 书/报告/会议事项章节会议稿件同行评审

摘要

A novel 3-bit 3rd-order ΔΣ fractional-N frequency synthesizer specialized for monolithic UHF band radio frequency identification reader is implemented in 0.18μm CMOS technology. The phase noise requirements are recapitulated for the zero-IF transceiver architecture and EPC global C1G2 and ETSI multi-protocol operation. The measurement results show that the synthesizer phase noise at 200 kHz offset is suppressed by the additional zero configuration in delta-sigma modulator (DSM)'s noise transfer function with acceptable in-band noise penalty. The measured phase noise is -102 and -126.5dBc/Hz at 200 kHz and 1 MHz offsets from 900 MHz operation frequency while drawing 9.6 mA from 1.8 V power supply.

源语言英语
主期刊名ASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC
545-548
页数4
DOI
出版状态已出版 - 2009
活动2009 8th IEEE International Conference on ASIC, ASICON 2009 - Changsha, 中国
期限: 20 10月 200923 10月 2009

出版系列

姓名ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC

会议

会议2009 8th IEEE International Conference on ASIC, ASICON 2009
国家/地区中国
Changsha
时期20/10/0923/10/09

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