An Enhanced ASAP7 PDK with Power Via Technology for IR Drop and PPA Evaluation

This paper presents a redesign of the open-source 7 nm FinFET ASAP7 PDK to integrate PowerVia and backside metal technologies. We designed the backside metal stack and updated the technology files to include specifications for backside metal layers and vias. We developed comprehensive 6-track and 5-track standard cell libraries, each comprising 241 cells and incorporating PowerVia technology. Furthermore, we established a place-and-route flow that supports backside metals for largescale circuit-level evaluation. Experimental results show that the PV-6T library reduces chip-level area by 15%-18% and mitigates maximum static IR drop by 64%-79%, while the PV-5T library delivers 20% cell-level area scaling, 28%-32% chip-level area reduction and reduces maximum static IR drop by 71% 82%. Routing congestion is mitigated, enabling up to 94% core utilization, and the frequency is increased by 1.39 × in average.