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An Automatic Comparator Offset Calibration for High-Speed Flash ADCs in FDSOI CMOS Technology

  • Yulang Feng
  • , Qingjun Fan
  • , Hao Deng
  • , Jeffrey Chen
  • , Runxi Zhang
  • , Phaneendra Bikkina
  • , Jinghong Chen
  • University of Houston
  • St. Mark's School of Texas
  • Alphacore Inc

科研成果: 书/报告/会议事项章节会议稿件同行评审

摘要

This paper presents an automatic comparator offset calibration scheme for designing high-speed flash analog-to-digital data converters (ADCs). It leverages the threshold voltage control capability via back-gate in FDSOI CMOS technology and thus does not require extra transistor pairs or capacitive loads, avoiding comparator speed degradation. An automatic calibration approach employing a successive approximation algorithm (SAA) is also developed. The comparator along with the calibration circuit are designed in a 28-nm FDSOI CMOS process. Simulation results show that the design achieves a resolution of 1.84 mV and a calibration range of ±58 mV with a power consumption of 440 μW under a 1V power supply.

源语言英语
主期刊名2020 IEEE 11th Latin American Symposium on Circuits and Systems, LASCAS 2020
出版商Institute of Electrical and Electronics Engineers Inc.
ISBN(电子版)9781728134277
DOI
出版状态已出版 - 2月 2020
活动11th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2020 - San Jose, 哥斯达黎加
期限: 25 2月 202028 2月 2020

出版系列

姓名2020 IEEE 11th Latin American Symposium on Circuits and Systems, LASCAS 2020

会议

会议11th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2020
国家/地区哥斯达黎加
San Jose
时期25/02/2028/02/20

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