TY - JOUR
T1 - Accurate SPICE Modeling of Poly-silicon Resistor in 40nm CMOS Technology Process for Analog Circuit Simulation
AU - Sun, Lijie
AU - Li, Xiaojin
AU - Shi, Yanling
AU - Guo, Ao
AU - Liu, Linlin
AU - Hu, Shaojian
AU - Chen, Shoumian
AU - Zhao, Yuhang
AU - Shang, Ganbing
AU - Cheng, Jia
AU - Ding, Lin
N1 - Publisher Copyright:
© Owned by the authors, published by EDP Sciences, 2015.
PY - 2015/7/9
Y1 - 2015/7/9
N2 - In this paper, the SPICE model of poly resistor is accurately developed based on silicon data. To describe the non-linear R-V trend, the new correlation in temperature and voltage is found in non-silicide poly-silicon resistor. A scalable model is developed on the temperature-dependent characteristics (TDC) and the temperature-dependent voltage characteristics (TDVC) from the R-V data. Besides, the parasitic capacitance between poly and substrate are extracted from real silicon structure in replacing conventional simulation data. The capacitance data are tested through using on-wafer charge-induced-injection error-free charge-based capacitance measurement (CIEF-CBCM) technique which is driven by non-overlapping clock generation circuit. All modeling test structures are designed and fabricated through using 40nm CMOS technology process. The new SPICE model of poly-silicon resistor is more accurate to silicon for analog circuit simulation.
AB - In this paper, the SPICE model of poly resistor is accurately developed based on silicon data. To describe the non-linear R-V trend, the new correlation in temperature and voltage is found in non-silicide poly-silicon resistor. A scalable model is developed on the temperature-dependent characteristics (TDC) and the temperature-dependent voltage characteristics (TDVC) from the R-V data. Besides, the parasitic capacitance between poly and substrate are extracted from real silicon structure in replacing conventional simulation data. The capacitance data are tested through using on-wafer charge-induced-injection error-free charge-based capacitance measurement (CIEF-CBCM) technique which is driven by non-overlapping clock generation circuit. All modeling test structures are designed and fabricated through using 40nm CMOS technology process. The new SPICE model of poly-silicon resistor is more accurate to silicon for analog circuit simulation.
KW - Parasitic capacitance
KW - Poly-silicon resistor
KW - SPICE model
KW - Temperature-dependent voltage characteristics (TDVC)
UR - https://www.scopus.com/pages/publications/84943738249
U2 - 10.1051/matecconf/20152202023
DO - 10.1051/matecconf/20152202023
M3 - 会议文章
AN - SCOPUS:84943738249
SN - 2261-236X
VL - 22
JO - MATEC Web of Conferences
JF - MATEC Web of Conferences
M1 - 02023
T2 - International Conference on Engineering Technology and Application, ICETA 2015
Y2 - 29 May 2015 through 30 May 2015
ER -