A novel hardware trojan detection technique using heuristic partition and test pattern generation

A novel hardware Trojan detection method based on heuristic partition and optimal test pattern generation is proposed. First, we use a scan cell distribution based heuristic partition to divide the circuit into regions. Then, we propose a test vector ordering algorithm to generate near-optimal test patterns based on the circuit's structure. Lastly, we activate each region separately and perform localized I_DDT analysis to detect hardware Trojans while a signal calibration technique is used to eliminate the effect of process variations and noises. The benefits of this approach are that it can magnify detection sensitivity, eliminate the effects of process variations and noises, ensure the scalability of hardware Trojan detection facing large scale ICs, and determine Trojan's location. We evaluate our approach on benchmark circuits and the experiment results show that the detection sensitivity is greatly improved.