A high-linear PLL-based FMCW frequency synthesizer with 42-kHz rms FM error and 1.2-GHz chirp bandwidth

This article presents a high-linear phase-locked-loop-based (PLL-based) frequency-modulated continuous-wave (FMCW) frequency synthesizer for 77 GHz automotive radar applications. A behavioral model of the rms FM error by constructing the PLL transient response under a unit frequency step and taking into account the slope of the chirp signal is developed. Simulation results demonstrate the effectiveness of the proposed model in optimizing chirp linearity. The behavioral model is used to facilitate the design of the 77 GHzFMCWsynthesizer fabricated in a 55 nm CMOS process. A gain linearized varactor approach is also developed to linearize the voltage-controlled oscillator (VCO) gain (KVCO) to ensure constant PLL bandwidth maintaining optimum chirp linearity. Measurement results show that the synthesizer achieves a 1.2 GHz chirp bandwidth, a minimum rms FM error of 42 kHz (0.0035% of the chirp bandwidth) under a 4.219 MHz/μs chirp slope while consuming 74.6mW of power. The measured integer-N mode and fractional-N mode phase noises normalized to 78 GHz are -81:6 dBc/Hz and -80:1 dBc/Hz at 1MHz offset, respectively.