A comprehensive power evaluation of CMOS full adders

This paper presents a comprehensive summary and evaluation of one bit full adders. In total, 32 adders in different logic styles have been implemented and evaluated under one uniform environment, while previous studies have evaluated at most 8 adders. Problems with previous performance studies on full adders have been identified. The results presented here can also resolve conflicting results reported in literature. The collected data indicate that certain evaluation experiment conditions can affect the evaluation results obtained. A few adders consistently consume a large amount of power under all different simulation conditions. On the other hand, some unconventionally designed 10-transistor adders consistently consume less power than the rest of the adders do.