TY - GEN
T1 - A Compact Broadband Power Amplifier with High Efficiency and <1% Power-Added Efficiency Variation over 24-36 GHz
AU - Qian, Yunhan
AU - Tao, Yu
AU - Shi, Chunqi
AU - Huang, Leilei
AU - Chen, Jinghong
AU - Zhang, Runxi
N1 - Publisher Copyright:
© 2026 IEEE.
PY - 2026
Y1 - 2026
N2 - This paper presents a compact broadband and high-efficiency power amplifier (PA) for fifth-generation (5G) new radio (NR) frequency range 2 (FR2) communications. Using a class-B PA as an example, the mechanism behind inherent power-added efficiency (PAE) non-flatness in conventional cascode architectures is analyzed. To address this, the design incorporates a parallel inter-stage inductor, which effectively mitigates non-ideal effects in traditional cascode structures. The proposed architecture improves the output impedance matching, resolving the degraded S22 performance in conventional cascode PAs at saturation power (Psat). This enhancement makes the design more suitable for phased-array applications. Furthermore, a compact low-coupling transformer is implemented to minimize chip area. Designed in a 40 nm CMOS, the PA achieves 19.27 dBm Psat with a 3 dB bandwidth spanning 21-38 GHz. Within 22.5-38 GHz, the Psat variation remains below 1 dB. The PAE variation is maintained within <1% from 24-36 GHz. The core area occupies only 0.089 mm2.
AB - This paper presents a compact broadband and high-efficiency power amplifier (PA) for fifth-generation (5G) new radio (NR) frequency range 2 (FR2) communications. Using a class-B PA as an example, the mechanism behind inherent power-added efficiency (PAE) non-flatness in conventional cascode architectures is analyzed. To address this, the design incorporates a parallel inter-stage inductor, which effectively mitigates non-ideal effects in traditional cascode structures. The proposed architecture improves the output impedance matching, resolving the degraded S22 performance in conventional cascode PAs at saturation power (Psat). This enhancement makes the design more suitable for phased-array applications. Furthermore, a compact low-coupling transformer is implemented to minimize chip area. Designed in a 40 nm CMOS, the PA achieves 19.27 dBm Psat with a 3 dB bandwidth spanning 21-38 GHz. Within 22.5-38 GHz, the Psat variation remains below 1 dB. The PAE variation is maintained within <1% from 24-36 GHz. The core area occupies only 0.089 mm2.
KW - Broadband
KW - Fifth generation (5G)
KW - Frequency range 2 (FR2)
KW - High-efficiency
KW - New radio (NR)
KW - Power amplifier (PA)
KW - Power-added efficiency (PAE)
UR - https://www.scopus.com/pages/publications/105043431061
U2 - 10.1109/ISCAS66217.2026.11562411
DO - 10.1109/ISCAS66217.2026.11562411
M3 - 会议稿件
AN - SCOPUS:105043431061
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 25
EP - 29
BT - ISCAS 2026 - 2026 IEEE International Symposium on Circuits and Systems
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2026 IEEE International Symposium on Circuits and Systems, ISCAS 2026
Y2 - 24 May 2026 through 27 May 2026
ER -