TY - GEN
T1 - A Clock Delivery Path with Peaking Buffers for 112Gb/s Wireline Transceiver
AU - Zhou, Hang
AU - Ye, Bingyi
AU - Gai, Weixin
N1 - Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - With the ever-increasing demand of higher wireline data rates in recent years, long-range on-chip clock delivery for multiple transceivers (TRX) is underway, in which DC offset is accumulated through multistage clock buffers, causing quadrature error and inducing deterministic jitter that degrades bit error rate. This paper presents a clock delivery path design for 112Gb/s wireline transceivers, in which peaking buffers suppress DC offset to realize lower quadrature error. Remaining error is then dealt with by capacitor-DAC based quadrature-error canceller (QEC). Implemented in 28nm CMOS process, the quadrature error in proposed clock path achieves a standard deviation of 1.61°. The QEC provides a +/-6.55° tuning range with a step of 0.94°.
AB - With the ever-increasing demand of higher wireline data rates in recent years, long-range on-chip clock delivery for multiple transceivers (TRX) is underway, in which DC offset is accumulated through multistage clock buffers, causing quadrature error and inducing deterministic jitter that degrades bit error rate. This paper presents a clock delivery path design for 112Gb/s wireline transceivers, in which peaking buffers suppress DC offset to realize lower quadrature error. Remaining error is then dealt with by capacitor-DAC based quadrature-error canceller (QEC). Implemented in 28nm CMOS process, the quadrature error in proposed clock path achieves a standard deviation of 1.61°. The QEC provides a +/-6.55° tuning range with a step of 0.94°.
KW - DC offset
KW - clock delivery
KW - quadrature error canceller
KW - wireline transceiver
UR - https://www.scopus.com/pages/publications/85147250603
U2 - 10.1109/ICICM56102.2022.10011239
DO - 10.1109/ICICM56102.2022.10011239
M3 - 会议稿件
AN - SCOPUS:85147250603
T3 - 2022 7th International Conference on Integrated Circuits and Microsystems, ICICM 2022
SP - 377
EP - 381
BT - 2022 7th International Conference on Integrated Circuits and Microsystems, ICICM 2022
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 7th International Conference on Integrated Circuits and Microsystems, ICICM 2022
Y2 - 28 October 2022 through 31 October 2022
ER -