A 500 MS/s 10-Bit Single-Channel SAR ADC with A Double-Rate Comparator

Qingjun Fan; Runxi Zhang; Phaneendra Bikkina; Esko Mikkola; Jinghong Chen

doi:10.1109/ESSCIRC.2019.8902706

A 500 MS/s 10-Bit Single-Channel SAR ADC with A Double-Rate Comparator

Qingjun Fan^*
, Runxi Zhang
, Phaneendra Bikkina
, Esko Mikkola
, Jinghong Chen

^*此作品的通讯作者

通信与电子工程学院

University of Houston
Alphacore Inc

科研成果: 书/报告/会议事项章节 › 会议稿件 › 同行评审

5 引用（Scopus）

摘要

This paper presents a 500 MS/s 10-bit single-channel SAR ADC with a reconfigurable double-rate comparator for enhanced operation speed. The proposed double-rate comparator effectively eliminates the delay caused by comparator reset from the critical path while consuming less power and reducing the clock frequency by half. A test chip is fabricated in a 28 nm FDSOI technology. Clocked at 500 MS/s,the proposed ADC achieves a SNDR of 52.7 dB and a SFDR of 62.49 dB at Nyquist with a power consumption of 1.18 mW,showing a Walden FOM of 6.7 fJ/conv.-step.

源语言	英语
主期刊名	ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference
出版商	Institute of Electrical and Electronics Engineers Inc.
页	193-196
页数	4
ISBN（电子版）	9781728115504
DOI	https://doi.org/10.1109/ESSCIRC.2019.8902706
出版状态	已出版 - 9月 2019
活动	45th IEEE European Solid State Circuits Conference, ESSCIRC 2019 - Cracow, 波兰期限: 23 9月 2019 → 26 9月 2019

丛书

姓名	ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference

会议

会议	45th IEEE European Solid State Circuits Conference, ESSCIRC 2019
国家/地区	波兰
市	Cracow
时期	23/09/19 → 26/09/19

访问文件

10.1109/ESSCIRC.2019.8902706

其它文件与链接

链接到 Scopus 的出版物

引用此

Fan, Q., Zhang, R., Bikkina, P., Mikkola, E., & Chen, J. (2019). A 500 MS/s 10-Bit Single-Channel SAR ADC with A Double-Rate Comparator. 在 ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (页码 193-196). 期刊论文 8902706 (ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ESSCIRC.2019.8902706

@inproceedings{bdadcdd9769e40b4838be247bf0ac686,

title = "A 500 MS/s 10-Bit Single-Channel SAR ADC with A Double-Rate Comparator",

abstract = "This paper presents a 500 MS/s 10-bit single-channel SAR ADC with a reconfigurable double-rate comparator for enhanced operation speed. The proposed double-rate comparator effectively eliminates the delay caused by comparator reset from the critical path while consuming less power and reducing the clock frequency by half. A test chip is fabricated in a 28 nm FDSOI technology. Clocked at 500 MS/s,the proposed ADC achieves a SNDR of 52.7 dB and a SFDR of 62.49 dB at Nyquist with a power consumption of 1.18 mW,showing a Walden FOM of 6.7 fJ/conv.-step.",

author = "Qingjun Fan and Runxi Zhang and Phaneendra Bikkina and Esko Mikkola and Jinghong Chen",

note = "Publisher Copyright: {\textcopyright} 2019 IEEE.; 45th IEEE European Solid State Circuits Conference, ESSCIRC 2019 ; Conference date: 23-09-2019 Through 26-09-2019",

year = "2019",

month = sep,

doi = "10.1109/ESSCIRC.2019.8902706",

language = "英语",

series = "ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "193--196",

booktitle = "ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference",

address = "美国",

}

Fan, Q, Zhang, R, Bikkina, P, Mikkola, E & Chen, J 2019, A 500 MS/s 10-Bit Single-Channel SAR ADC with A Double-Rate Comparator. 在 ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference., 8902706, ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference, Institute of Electrical and Electronics Engineers Inc., 页码 193-196, 45th IEEE European Solid State Circuits Conference, ESSCIRC 2019, Cracow, 波兰, 23/09/19. https://doi.org/10.1109/ESSCIRC.2019.8902706

A 500 MS/s 10-Bit Single-Channel SAR ADC with A Double-Rate Comparator. / Fan, Qingjun; Zhang, Runxi; Bikkina, Phaneendra 等.
ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference. Institute of Electrical and Electronics Engineers Inc., 2019. 页码 193-196 8902706 (ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference).

科研成果: 书/报告/会议事项章节 › 会议稿件 › 同行评审

TY - GEN

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AU - Fan, Qingjun

AU - Zhang, Runxi

AU - Bikkina, Phaneendra

AU - Mikkola, Esko

AU - Chen, Jinghong

PY - 2019/9

Y1 - 2019/9

N2 - This paper presents a 500 MS/s 10-bit single-channel SAR ADC with a reconfigurable double-rate comparator for enhanced operation speed. The proposed double-rate comparator effectively eliminates the delay caused by comparator reset from the critical path while consuming less power and reducing the clock frequency by half. A test chip is fabricated in a 28 nm FDSOI technology. Clocked at 500 MS/s,the proposed ADC achieves a SNDR of 52.7 dB and a SFDR of 62.49 dB at Nyquist with a power consumption of 1.18 mW,showing a Walden FOM of 6.7 fJ/conv.-step.

AB - This paper presents a 500 MS/s 10-bit single-channel SAR ADC with a reconfigurable double-rate comparator for enhanced operation speed. The proposed double-rate comparator effectively eliminates the delay caused by comparator reset from the critical path while consuming less power and reducing the clock frequency by half. A test chip is fabricated in a 28 nm FDSOI technology. Clocked at 500 MS/s,the proposed ADC achieves a SNDR of 52.7 dB and a SFDR of 62.49 dB at Nyquist with a power consumption of 1.18 mW,showing a Walden FOM of 6.7 fJ/conv.-step.

UR - https://www.scopus.com/pages/publications/85075933991

U2 - 10.1109/ESSCIRC.2019.8902706

DO - 10.1109/ESSCIRC.2019.8902706

M3 - 会议稿件

AN - SCOPUS:85075933991

T3 - ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference

SP - 193

EP - 196

BT - ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 45th IEEE European Solid State Circuits Conference, ESSCIRC 2019

Y2 - 23 September 2019 through 26 September 2019

ER -

Fan Q, Zhang R, Bikkina P, Mikkola E, Chen J. A 500 MS/s 10-Bit Single-Channel SAR ADC with A Double-Rate Comparator. 在 ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference. Institute of Electrical and Electronics Engineers Inc. 2019. 页码 193-196. 8902706. (ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference). doi: 10.1109/ESSCIRC.2019.8902706

A 500 MS/s 10-Bit Single-Channel SAR ADC with A Double-Rate Comparator

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