A 400-MS/s 10-Bit SAR-Assisted Two-Step Digital-Slope ADC

This paper presents a successive-approximation register (SAR)-assisted two-step digital-slope analog-to-digital converter (ADC), which takes advantage of both the moderate conversion speed of the SAR ADC and the low noise characteristic of the digital-slope ADC. To improve the digital-slope ADC conversion speed while maintaining its power efficiency benefit, a novel architecture with a 5-bit SAR ADC as the coarse stage and a 6-bit two-step digital-slope ADC as the fine stage is proposed. A charge-sharing-based implementation of the twostep digital-slope ADC eliminates the need for power-consuming on-chip reference buffers and residue calibrations between the SAR and digital slope stages. Designed and simulated in a 55 nm CMOS technology, the proposed ADC achieves an SNDR of 56.27 dB at 400 MS/s while dissipating 2.4 mW, leading to a FOM of 11.24 fJ/conv.-step.