A 3 mW 1.2-3.6 GHz Multi-Phase PLL-Based Clock Generator with TDC Assisted Auto-Calibration of Loop Bandwidth

A PLL-based clock generator with an auto-calibration circuit is presented. The auto-calibration circuit employs an oscillator-based time-to-digital converter (TDC) to achieve a constant loop bandwidth and fast lock time. The TDC measures the operating frequency of M-stage ring-VCO with a resolution of fREF/(k·2M) in a time period of k·TREF. The measured frequency is utilized to calibrate loop bandwidth and VCO frequency. The clock generator is designed in 40nm CMOS process and operates from 1.2GHz to 3.6GHz with 8-phase outputs. The total lock time is less than 3μs including calibration and PLL closed-loop locking processes. Operating at 3.2GHz, the in-band phase noise is better than -99.4dBc/Hz and root-mean square (RMS) jitter integrated from 10KHz to 100MHz is 2 ps. In the entire operating range, the RMS jitter and reference spur are better than 5.5ps and -68.5dBc/Hz, respectively. The clock generator consumes only 3mW from 1.1V supply at high-frequency end and 1.6mW at low-frequency end. The active area is only 0.04mm² including on-chip loop filter and auto-calibration circuits.