@inproceedings{51fbb844e21b4e5c864435d649cc609e,
title = "A 25Gb/s 185mW PAM-4 receiver with 4-tap adaptive DFE and sampling clock optimization in 55nm CMOS",
abstract = "A 25Gb/s PAM-4 receiver is presented with 4-tap adaptive DFE and sampling clock optimization. PAM-4 signaling suffers more from non-optimal sampling clock phase which degrades BER. By finding the point with the least pre-cursor ISI, the sampling clock can be recovered with optimal phase, which improves the BER by as much as 109 through 12.5dB channel loss. A novel clocked amplifier is implemented as a slicer to reduce the loop delay and meet the timing constraints of the direct feedback. Fabricated in 55nm CMOS technology, the receiver occupies 0.27mm2 and consumes 185mW at 25Gb/s with a power supply of 1.2V.",
keywords = "Clock, Clock phase optimization, Data recovery, PAM4, Wireline receiver",
author = "Liangxiao Tang and Weixin Gai and Yang, \{Chih Kong Ken\} and Bingyi Ye and Congcong Chen",
note = "Publisher Copyright: {\textcopyright} 2021 IEEE; 53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021 ; Conference date: 22-05-2021 Through 28-05-2021",
year = "2021",
doi = "10.1109/ISCAS51556.2021.9401299",
language = "英语",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings",
address = "美国",
}