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A 256-Channel, 3.49-mW Wireless Neural Recording SoC with Adaptive Delta Compression and Error-Resilient Coding

  • Wenxian Gu
  • , Liangjian Lyu*
  • , Zepeng Huang
  • , Yingfei Xiang
  • , Sirou Li
  • , Wenjun Gong
  • , Xing Wu
  • , C. J.Richard Shi
  • *此作品的通讯作者
  • East China Normal University
  • Fudan University
  • University of Washington

科研成果: 书/报告/会议事项章节 › 会议稿件 › 同行评审

摘要

This paper presents a fully-integrated 256-channel wireless wideband neural-recording SoC that integrates AFEs with distributed neural processors and a low-power bidirectional transceiver. A nearlossless adaptive-delta algorithm reduces data rate by 60% while preserving features. A power-efficient tri-state bus enables streamlined transfer. The 3.2 GHz/433 MHz OOK links with hybrid error-resilient coding boost reliability. Fabricated in 65 nm CMOS, this SoC consumes 3.49 mW at 1.2 V and supports 30 kHz/channel.

源语言英语
主期刊名2026 IEEE Custom Integrated Circuits Conference, CICC 2026 - Proceedings
出版商Institute of Electrical and Electronics Engineers Inc.
ISBN(电子版)9798331572105
DOI
出版状态已出版 - 2026
活动46th Annual IEEE Custom Integrated Circuits Conference, CICC 2026 - Seattle, 美国
期限: 19 4月 2026 → 23 4月 2026

丛书

姓名Proceedings of the Custom Integrated Circuits Conference
ISSN(印刷版)0886-5930

会议

会议46th Annual IEEE Custom Integrated Circuits Conference, CICC 2026
国家/地区美国
市Seattle
时期19/04/26 → 23/04/26

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