摘要
This brief presents a 24 GHz dual-mode frequency synthesizer designed in a 55-nm CMOS technology supporting both Doppler and frequency modulated continuous wave (FMCW) radars. The effects of chirp linearity and delta-sigma modulation (DSM) resolution on the rms FM error is analyzed. A design procedure for the PLL loop bandwidth and time interval of the frequency step to reduce the rms FM error is proposed. A voltage-controlled oscillator (VCO) featuring a four-coil transformer load is developed providing differential local oscillation (LO) signals for the transmitter (TX) and quadrature LO signals for the 2-channel receiver (RX). The prototype is designed with a loop bandwidth of 350 kHz, a frequency step time interval of 2 μ s, and a VCO tuning linearity of 26%. In the FMCW mode, it achieved an rms FM error of 68.8 kHz over a 1.25 GHz chirp bandwidth. In the Doppler mode, the VCO operates in the free-running mode to save power consumption. An 8-bit digital-to-analog converter (DAC) is used to provide the VCO control voltage compensating process and voltage variations. The free-running VCO operates at a 24.125 GHz and has a frequency error of less than 1 MHz.
| 源语言 | 英语 |
|---|---|
| 页(从-至) | 2518-2522 |
| 页数 | 5 |
| 期刊 | IEEE Transactions on Circuits and Systems II: Express Briefs |
| 卷 | 69 |
| 期 | 5 |
| DOI | |
| 出版状态 | 已出版 - 1 5月 2022 |
指纹
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