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A 200-Gb/s PAM-4 Transmitter with 1.6-Vppd Output Swing and Clock Skew Correction in 12-nm FinFET

  • Boyang Zhang
  • , Zhifei Wang
  • , Zeze Feng
  • , Tianchen Ye
  • , Bingyi Ye
  • , Zixu Wang
  • , Weixin Gai*
  • *此作品的通讯作者
  • Peking University
  • Beijing Advanced Innovation Center for Integrated Circuits

科研成果: 书/报告/会议事项章节会议稿件同行评审

摘要

This work demonstrates a 200-Gb/s PAM-4 transmitter with 1.6-Vppd output swing in 12-nm FinFET technology. Novel pulse generators are proposed to reduce jitter by two orders of magnitude. The quadrature clock generator is capable of detecting and correcting three types of clock skews including duty-cycle error, quadrature error, and differential error. The power efficiency of the transmitter is 3.32 pJ/bit and the active area is 0.116

源语言英语
主期刊名2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024
出版商Institute of Electrical and Electronics Engineers Inc.
ISBN(电子版)9798350361469
DOI
出版状态已出版 - 2024
已对外发布
活动2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024 - Honolulu, 美国
期限: 16 6月 202420 6月 2024

出版系列

姓名Digest of Technical Papers - Symposium on VLSI Technology
ISSN(印刷版)0743-1562

会议

会议2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024
国家/地区美国
Honolulu
时期16/06/2420/06/24

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