@inproceedings{37382c15dc134905bb29050e63981758,
title = "A 13.6-17.7 GHz Sub-Harmonic Injection-Locked SSPLL with 74-fs RMS Jitter",
abstract = "This paper presents a sub-harmonic injection-locked sub-sampling PLL (SIL-SSPLL) that realizes a peaking-free jitter transfer. The use of an injection-locked oscillator (ILO) in SSPLL allows the PLL open-loop transfer function to achieve a higher phase margin, thereby enhancing the jitter performance. The study also analyzes the effects of injection locking strength on noise rejection for both the reference signal and the VCO showing that optimal jitter performance can be achieved by properly setting the injection strength. A 13.6 to 17.7 GHz SIL-SSPLL prototype fabricated in a 40 nm CMOS technology demonstrates 74 fs RMS integrated jitter at 15.8 GHz while consuming 22.6 mW of power, leading to an excellent figure of merit (FoM) of -249.1 dBc/Hz.",
keywords = "PLL, injection-locked PLL, injection-locked oscillator, phase noise, sub-sampling PLL",
author = "Yuri Lu and Chunqi Shi and Leilei Huang and Runxi Zhang and Hao Deng and Jinghong Chen",
note = "Publisher Copyright: {\textcopyright} 2025 IEEE.; 2025 IEEE International Symposium on Circuits and Systems, ISCAS 2025 ; Conference date: 25-05-2025 Through 28-05-2025",
year = "2025",
doi = "10.1109/ISCAS56072.2025.11044047",
language = "英语",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "ISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings",
address = "美国",
}