A 112Gb/s/wire Single-Ended Simultaneous Bi-Directional Transceiver with Dynamic Equalizer for Die-to-Die Interface in 28nm CMOS

Zhiwen Huang; Zhifei Wang; Bingyi Ye; Tianchen Ye; Dunshan Yu; Wei Wang; Weixin Gai

doi:10.1109/ISSCC49663.2026.11409095

A 112Gb/s/wire Single-Ended Simultaneous Bi-Directional Transceiver with Dynamic Equalizer for Die-to-Die Interface in 28nm CMOS

Zhiwen Huang
, Zhifei Wang
, Bingyi Ye
, Tianchen Ye
, Dunshan Yu
, Wei Wang
, Weixin Gai

通信与电子工程学院

Peking University
Beijing Advanced Innovation Center for Integrated Circuits

科研成果: 书/报告/会议事项章节 › 会议稿件 › 同行评审

摘要

This work presents an 8-lane 112Gb/s/wire single-ended simultaneous bi-directional transceiver with a 3mm shield-less on-chip channel. A dynamic equalizer is proposed to decouple the bi-directional signals, and compensate for insertion loss and crosstalk. Fabricated in 28nm CMOS, the transceiver achieves a BER of less than 10^-14, and an energy efficiency of 1.01pJ/b.

源语言	英语
主期刊名	2026 IEEE International Solid-State Circuits Conference, ISSCC 2026
出版商	Institute of Electrical and Electronics Engineers Inc.
页	140-142
页数	3
ISBN（电子版）	9798331589363
DOI	https://doi.org/10.1109/ISSCC49663.2026.11409095
出版状态	已出版 - 2026
活动	2026 IEEE International Solid-State Circuits Conference, ISSCC 2026 - San Francisco, 美国期限: 15 2月 2026 → 19 2月 2026

出版系列

姓名	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
卷	69
ISSN（印刷版）	0193-6530

会议

会议	2026 IEEE International Solid-State Circuits Conference, ISSCC 2026
国家/地区	美国
市	San Francisco
时期	15/02/26 → 19/02/26

联合国可持续发展目标

此成果有助于实现下列可持续发展目标：

可持续发展目标 7 经济适用的清洁能源

访问文件

10.1109/ISSCC49663.2026.11409095

其它文件与链接

链接到 Scopus 的出版物

引用此

Huang, Z., Wang, Z., Ye, B., Ye, T., Yu, D., Wang, W., & Gai, W. (2026). A 112Gb/s/wire Single-Ended Simultaneous Bi-Directional Transceiver with Dynamic Equalizer for Die-to-Die Interface in 28nm CMOS. 在 2026 IEEE International Solid-State Circuits Conference, ISSCC 2026 (页码 140-142). (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; 卷 69). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC49663.2026.11409095

Huang, Zhiwen ; Wang, Zhifei ; Ye, Bingyi 等. / A 112Gb/s/wire Single-Ended Simultaneous Bi-Directional Transceiver with Dynamic Equalizer for Die-to-Die Interface in 28nm CMOS. 2026 IEEE International Solid-State Circuits Conference, ISSCC 2026. Institute of Electrical and Electronics Engineers Inc., 2026. 页码 140-142 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

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title = "A 112Gb/s/wire Single-Ended Simultaneous Bi-Directional Transceiver with Dynamic Equalizer for Die-to-Die Interface in 28nm CMOS",

abstract = "This work presents an 8-lane 112Gb/s/wire single-ended simultaneous bi-directional transceiver with a 3mm shield-less on-chip channel. A dynamic equalizer is proposed to decouple the bi-directional signals, and compensate for insertion loss and crosstalk. Fabricated in 28nm CMOS, the transceiver achieves a BER of less than 10-14, and an energy efficiency of 1.01pJ/b.",

author = "Zhiwen Huang and Zhifei Wang and Bingyi Ye and Tianchen Ye and Dunshan Yu and Wei Wang and Weixin Gai",

note = "Publisher Copyright: {\textcopyright} 2026 IEEE.; 2026 IEEE International Solid-State Circuits Conference, ISSCC 2026 ; Conference date: 15-02-2026 Through 19-02-2026",

year = "2026",

doi = "10.1109/ISSCC49663.2026.11409095",

language = "英语",

series = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "140--142",

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}

Huang, Z, Wang, Z, Ye, B, Ye, T, Yu, D, Wang, W & Gai, W 2026, A 112Gb/s/wire Single-Ended Simultaneous Bi-Directional Transceiver with Dynamic Equalizer for Die-to-Die Interface in 28nm CMOS. 在 2026 IEEE International Solid-State Circuits Conference, ISSCC 2026. Digest of Technical Papers - IEEE International Solid-State Circuits Conference, 卷 69, Institute of Electrical and Electronics Engineers Inc., 页码 140-142, 2026 IEEE International Solid-State Circuits Conference, ISSCC 2026, San Francisco, 美国, 15/02/26. https://doi.org/10.1109/ISSCC49663.2026.11409095

A 112Gb/s/wire Single-Ended Simultaneous Bi-Directional Transceiver with Dynamic Equalizer for Die-to-Die Interface in 28nm CMOS. / Huang, Zhiwen; Wang, Zhifei; Ye, Bingyi 等.
2026 IEEE International Solid-State Circuits Conference, ISSCC 2026. Institute of Electrical and Electronics Engineers Inc., 2026. 页码 140-142 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; 卷 69).

科研成果: 书/报告/会议事项章节 › 会议稿件 › 同行评审

TY - GEN

T1 - A 112Gb/s/wire Single-Ended Simultaneous Bi-Directional Transceiver with Dynamic Equalizer for Die-to-Die Interface in 28nm CMOS

AU - Huang, Zhiwen

AU - Wang, Zhifei

AU - Ye, Bingyi

AU - Ye, Tianchen

AU - Yu, Dunshan

AU - Wang, Wei

AU - Gai, Weixin

PY - 2026

Y1 - 2026

N2 - This work presents an 8-lane 112Gb/s/wire single-ended simultaneous bi-directional transceiver with a 3mm shield-less on-chip channel. A dynamic equalizer is proposed to decouple the bi-directional signals, and compensate for insertion loss and crosstalk. Fabricated in 28nm CMOS, the transceiver achieves a BER of less than 10-14, and an energy efficiency of 1.01pJ/b.

AB - This work presents an 8-lane 112Gb/s/wire single-ended simultaneous bi-directional transceiver with a 3mm shield-less on-chip channel. A dynamic equalizer is proposed to decouple the bi-directional signals, and compensate for insertion loss and crosstalk. Fabricated in 28nm CMOS, the transceiver achieves a BER of less than 10-14, and an energy efficiency of 1.01pJ/b.

UR - https://www.scopus.com/pages/publications/105035333386

U2 - 10.1109/ISSCC49663.2026.11409095

DO - 10.1109/ISSCC49663.2026.11409095

M3 - 会议稿件

AN - SCOPUS:105035333386

T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

SP - 140

EP - 142

BT - 2026 IEEE International Solid-State Circuits Conference, ISSCC 2026

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2026 IEEE International Solid-State Circuits Conference, ISSCC 2026

Y2 - 15 February 2026 through 19 February 2026

ER -

Huang Z, Wang Z, Ye B, Ye T, Yu D, Wang W 等. A 112Gb/s/wire Single-Ended Simultaneous Bi-Directional Transceiver with Dynamic Equalizer for Die-to-Die Interface in 28nm CMOS. 在 2026 IEEE International Solid-State Circuits Conference, ISSCC 2026. Institute of Electrical and Electronics Engineers Inc. 2026. 页码 140-142. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). doi: 10.1109/ISSCC49663.2026.11409095

A 112Gb/s/wire Single-Ended Simultaneous Bi-Directional Transceiver with Dynamic Equalizer for Die-to-Die Interface in 28nm CMOS

摘要

出版系列

会议

联合国可持续发展目标

访问文件

其它文件与链接

指纹

引用此