3-D Modeling of Fringe Gate Capacitance in Complementary FET (CFET)

In this work, an analytical model for fringe gate capacitance in complementary FET (CFET) is proposed. Three kinds of CFET based on the fin, gate-all-around (GAA) nanowire, and nanosheet are investigated. The fringe capacitance of CFET is separated into n- and p- FETs like dc performance. For each n- or p-FET, the fringe capacitances are divided into seven components according to the geometric topology. Conformal mapping and integral methods are used to calculate the dual- ${k}$ dielectric perpendicular capacitance and coplanar plate capacitance. The model accuracy is verified with the 3-D field solver. The impact of device parameters on the overall fringe gate capacitance is also evaluated. The proposed fringe gate capacitance model is implanted in the BSIM model and is verified for 3-D TCAD simulations. The proposed model is helpful for reducing the parasitic capacitance in CFET device design and CFET-based circuit design.