基于级间电容抵消技术的74~88 GHz高性能CMOS LNA设计

A 74-88 GHz high performance CMOS low noise amplifier (LNA) was designed and fabricated in 55 nm CMOS process for millimeter wave radar applications. The proposed LNA adopted cascode structure. In order to improve the noise figure and the stability gain, the inductive feedback common-gate-shorting technique with interstage parasitic capacitance cancellation and the out-of-phase dual-coupling g_m-boosting technique were adopted. Compared with the traditional common grid shorting technology, the inductive feedback common grid shorting technology with interstage parasitic capacitance cancellation improves the noise figure by 1.58 dB and the stability gain by 7.67 dB. The measurement results show that the peak gain of the LNA is of 17.1 dB, the minimum noise figure is 6.3 dB, the BW_-3dB is 14 GHz (74.8-88.8 GHz). The input 1 dB compression point (IP_1dB) is -10.2 dBm at a center frequency of 78 GHz while consuming 102 mW of power.