@inproceedings{fa0e4528a99846098e1ed3ef264f890e,
title = "Work-in-Progress: From Logical Time Scheduling to Real-Time Scheduling",
abstract = "Scheduling is a central yet challenging problem in real-time embedded systems. The Clock Constraint Specification Language (CCSL) provides a formalism to specify logical constraints of events in real-time embedded systems. A prerequisite for the events is that they must be schedulable under constraints. That is, there must be a schedule which controls all events to occur infinitely often. Schedulability analysis of CCSL raises important algorithmic problems such as computational complexity and design of efficient decision procedures. In this work, we compare the scheduling problems of CCSL specifications to the real-time scheduling problem. We show how to encode a simple task model in CCSL and discuss some benefits and differences compared to more classical scheduling strategies.",
keywords = "Logical Time, Schedulability, Time Model",
author = "Fr{\'e}d{\'e}ric Mallet and Min Zhang",
note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 39th IEEE Real-Time Systems Symposium, RTSS 2018 ; Conference date: 11-12-2018 Through 14-12-2018",
year = "2019",
month = jan,
day = "4",
doi = "10.1109/RTSS.2018.00025",
language = "英语",
series = "Proceedings - Real-Time Systems Symposium",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "143--146",
booktitle = "Proceedings - 39th IEEE Real-Time Systems Symposium, RTSS 2018",
address = "美国",
}