Work-in-progress: A PV aware data placement scheme for read performance improvement on LDPC based flash memory

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This paper proposes to improve read performance of LDPC based flash memory by exploiting process variation (PV). The work includes three parts. First, a block grouping approach is proposed to classify the flash blocks based on their reliability. Second, based on the grouping approach, a read data placement scheme is proposed, which is designed to place read-hot data on flash blocks with high reliability. However, simply placing read-hot data to high reliable blocks conflicts with recent PV-aware wear leveling schemes. In the third part of the work, a grouping partition scheme is proposed to limit the number of high reliable blocks for read-hot data. In this case, read performance can be well improved with little impact on the lifetime improvement.

Original languageEnglish
Title of host publicationProceedings of the 12th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, CODES 2017
PublisherAssociation for Computing Machinery, Inc
ISBN (Electronic)9781450351850
DOIs
StatePublished - 15 Oct 2017
Externally publishedYes
Event12th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES 2017 - Seoul, Korea, Republic of
Duration: 15 Oct 201720 Oct 2017

Publication series

NameProceedings of the 12th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, CODES 2017

Conference

Conference12th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES 2017
Country/TerritoryKorea, Republic of
CitySeoul
Period15/10/1720/10/17

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