V2Va: An Efficient Verilog-to-Verilog-A Translator for Accelerated Mixed-Signal Simulation

Yicong Shao; Chao Wang; Jiajie Huang; Wangzilu Lu; Zhiwen Gu; Longfan Li; Yuhang Zhang; Jian Zhao; Wei Mao; Yongfu Li

doi:10.1109/APCCAS60141.2023.00058

V2Va: An Efficient Verilog-to-Verilog-A Translator for Accelerated Mixed-Signal Simulation

Yicong Shao
, Chao Wang
, Jiajie Huang
, Wangzilu Lu
, Zhiwen Gu
, Longfan Li
, Yuhang Zhang
, Jian Zhao
, Wei Mao
, Yongfu Li^*

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

This paper introduces a streamlined Verilog-to-Verilog-A (V2Va) translation tool that automates the conversion of Verilog designs into Verilog-A, enabling concurrent simulation of analog and digital circuits. Through a set of mapping rules, V2Va facilitates mixed-signal simulations in an analog environment, negating the requirement for a separate mixed-signal simulation engine and overcoming multiple types of EDA licensing obstacles. Our methodology demonstrates a notable acceleration in mixed-signal simulation, surpassing 2 ×, underscoring its significant impact and applicability in the domain of circuit design.

Original language	English
Title of host publication	Proceedings - 2023 19th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2023
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	222-226
Number of pages	5
ISBN (Electronic)	9798350381191
DOIs	https://doi.org/10.1109/APCCAS60141.2023.00058
State	Published - 2023
Externally published	Yes
Event	19th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2023 - Hyderabad, India Duration: 19 Nov 2023 → 22 Nov 2023

Publication series

Name	Proceedings - 2023 19th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2023

Conference

Conference	19th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2023
Country/Territory	India
City	Hyderabad
Period	19/11/23 → 22/11/23

Keywords

Mixed-signal Simulation
Verilog
Verilog-A
abstract syntax tree
generator
translator

Access to Document

10.1109/APCCAS60141.2023.00058

Cite this

Shao, Y., Wang, C., Huang, J., Lu, W., Gu, Z., Li, L., Zhang, Y., Zhao, J., Mao, W., & Li, Y. (2023). V2Va: An Efficient Verilog-to-Verilog-A Translator for Accelerated Mixed-Signal Simulation. In Proceedings - 2023 19th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2023 (pp. 222-226). (Proceedings - 2023 19th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2023). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APCCAS60141.2023.00058

Shao, Yicong ; Wang, Chao ; Huang, Jiajie et al. / V2Va : An Efficient Verilog-to-Verilog-A Translator for Accelerated Mixed-Signal Simulation. Proceedings - 2023 19th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2023. Institute of Electrical and Electronics Engineers Inc., 2023. pp. 222-226 (Proceedings - 2023 19th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2023).

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title = "V2Va: An Efficient Verilog-to-Verilog-A Translator for Accelerated Mixed-Signal Simulation",

abstract = "This paper introduces a streamlined Verilog-to-Verilog-A (V2Va) translation tool that automates the conversion of Verilog designs into Verilog-A, enabling concurrent simulation of analog and digital circuits. Through a set of mapping rules, V2Va facilitates mixed-signal simulations in an analog environment, negating the requirement for a separate mixed-signal simulation engine and overcoming multiple types of EDA licensing obstacles. Our methodology demonstrates a notable acceleration in mixed-signal simulation, surpassing 2 ×, underscoring its significant impact and applicability in the domain of circuit design.",

keywords = "Mixed-signal Simulation, Verilog, Verilog-A, abstract syntax tree, generator, translator",

author = "Yicong Shao and Chao Wang and Jiajie Huang and Wangzilu Lu and Zhiwen Gu and Longfan Li and Yuhang Zhang and Jian Zhao and Wei Mao and Yongfu Li",

note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 19th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2023 ; Conference date: 19-11-2023 Through 22-11-2023",

year = "2023",

doi = "10.1109/APCCAS60141.2023.00058",

language = "英语",

series = "Proceedings - 2023 19th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2023",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "222--226",

booktitle = "Proceedings - 2023 19th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2023",

address = "美国",

}

Shao, Y, Wang, C, Huang, J, Lu, W, Gu, Z, Li, L, Zhang, Y, Zhao, J, Mao, W & Li, Y 2023, V2Va: An Efficient Verilog-to-Verilog-A Translator for Accelerated Mixed-Signal Simulation. in Proceedings - 2023 19th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2023. Proceedings - 2023 19th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2023, Institute of Electrical and Electronics Engineers Inc., pp. 222-226, 19th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2023, Hyderabad, India, 19/11/23. https://doi.org/10.1109/APCCAS60141.2023.00058

V2Va: An Efficient Verilog-to-Verilog-A Translator for Accelerated Mixed-Signal Simulation. / Shao, Yicong; Wang, Chao; Huang, Jiajie et al.
Proceedings - 2023 19th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2023. Institute of Electrical and Electronics Engineers Inc., 2023. p. 222-226 (Proceedings - 2023 19th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2023).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - V2Va

T2 - 19th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2023

AU - Shao, Yicong

AU - Wang, Chao

AU - Huang, Jiajie

AU - Lu, Wangzilu

AU - Gu, Zhiwen

AU - Li, Longfan

AU - Zhang, Yuhang

AU - Zhao, Jian

AU - Mao, Wei

AU - Li, Yongfu

PY - 2023

Y1 - 2023

N2 - This paper introduces a streamlined Verilog-to-Verilog-A (V2Va) translation tool that automates the conversion of Verilog designs into Verilog-A, enabling concurrent simulation of analog and digital circuits. Through a set of mapping rules, V2Va facilitates mixed-signal simulations in an analog environment, negating the requirement for a separate mixed-signal simulation engine and overcoming multiple types of EDA licensing obstacles. Our methodology demonstrates a notable acceleration in mixed-signal simulation, surpassing 2 ×, underscoring its significant impact and applicability in the domain of circuit design.

AB - This paper introduces a streamlined Verilog-to-Verilog-A (V2Va) translation tool that automates the conversion of Verilog designs into Verilog-A, enabling concurrent simulation of analog and digital circuits. Through a set of mapping rules, V2Va facilitates mixed-signal simulations in an analog environment, negating the requirement for a separate mixed-signal simulation engine and overcoming multiple types of EDA licensing obstacles. Our methodology demonstrates a notable acceleration in mixed-signal simulation, surpassing 2 ×, underscoring its significant impact and applicability in the domain of circuit design.

KW - Mixed-signal Simulation

KW - Verilog

KW - Verilog-A

KW - abstract syntax tree

KW - generator

KW - translator

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T3 - Proceedings - 2023 19th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2023

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BT - Proceedings - 2023 19th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2023

PB - Institute of Electrical and Electronics Engineers Inc.

Y2 - 19 November 2023 through 22 November 2023

ER -

Shao Y, Wang C, Huang J, Lu W, Gu Z, Li L et al. V2Va: An Efficient Verilog-to-Verilog-A Translator for Accelerated Mixed-Signal Simulation. In Proceedings - 2023 19th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2023. Institute of Electrical and Electronics Engineers Inc. 2023. p. 222-226. (Proceedings - 2023 19th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2023). doi: 10.1109/APCCAS60141.2023.00058

V2Va: An Efficient Verilog-to-Verilog-A Translator for Accelerated Mixed-Signal Simulation

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Keywords

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