USB2.0 endpoints controller in 180nm CMOS process

Yan Zhan; Li Kun Pan; Zhan Xia Zhao; Yong Hua Li; De Ming Wang; Zhong Quan Ma

USB2.0 endpoints controller in 180nm CMOS process

Yan Zhan^*
, Li Kun Pan
, Zhan Xia Zhao
, Yong Hua Li
, De Ming Wang
, Zhong Quan Ma

^*Corresponding author for this work

School of Physics and Electronic Science

Shanghai University

Research output: Contribution to journal › Article › peer-review

Abstract

The endpoints controller is designed in Verilog HDL forUSB2.0 device controller. It is user-configurable up to 16 endpoints. The endpoints controller supports 8-bit/16-bitUSB interface, 8-bit/16-bit/32-bitAHB or 8051 interface and 32-bitDMA interface. It is implemented in 180nm CMOS process and all functions have been proved by testing.

Original language	English
Pages (from-to)	389-393
Number of pages	5
Journal	Gongneng Cailiao yu Qijian Xuebao/Journal of Functional Materials and Devices
Volume	15
Issue number	4
State	Published - Aug 2009

Keywords

CMOS
Endpoints controller
USB2.0
VerilogHDL

Cite this

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title = "USB2.0 endpoints controller in 180nm CMOS process",

abstract = "The endpoints controller is designed in Verilog HDL forUSB2.0 device controller. It is user-configurable up to 16 endpoints. The endpoints controller supports 8-bit/16-bitUSB interface, 8-bit/16-bit/32-bitAHB or 8051 interface and 32-bitDMA interface. It is implemented in 180nm CMOS process and all functions have been proved by testing.",

keywords = "CMOS, Endpoints controller, USB2.0, VerilogHDL",

author = "Yan Zhan and Pan, \{Li Kun\} and Zhao, \{Zhan Xia\} and Li, \{Yong Hua\} and Wang, \{De Ming\} and Ma, \{Zhong Quan\}",

year = "2009",

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language = "英语",

volume = "15",

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journal = "Gongneng Cailiao yu Qijian Xuebao/Journal of Functional Materials and Devices",

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publisher = "Chinese Academy of Sciences",

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T1 - USB2.0 endpoints controller in 180nm CMOS process

AU - Zhan, Yan

AU - Pan, Li Kun

AU - Zhao, Zhan Xia

AU - Li, Yong Hua

AU - Wang, De Ming

AU - Ma, Zhong Quan

PY - 2009/8

Y1 - 2009/8

N2 - The endpoints controller is designed in Verilog HDL forUSB2.0 device controller. It is user-configurable up to 16 endpoints. The endpoints controller supports 8-bit/16-bitUSB interface, 8-bit/16-bit/32-bitAHB or 8051 interface and 32-bitDMA interface. It is implemented in 180nm CMOS process and all functions have been proved by testing.

AB - The endpoints controller is designed in Verilog HDL forUSB2.0 device controller. It is user-configurable up to 16 endpoints. The endpoints controller supports 8-bit/16-bitUSB interface, 8-bit/16-bit/32-bitAHB or 8051 interface and 32-bitDMA interface. It is implemented in 180nm CMOS process and all functions have been proved by testing.

KW - CMOS

KW - Endpoints controller

KW - USB2.0

KW - VerilogHDL

UR - https://www.scopus.com/pages/publications/84862112570

M3 - 文章

AN - SCOPUS:84862112570

SN - 1007-4252

VL - 15

SP - 389

EP - 393

JO - Gongneng Cailiao yu Qijian Xuebao/Journal of Functional Materials and Devices

JF - Gongneng Cailiao yu Qijian Xuebao/Journal of Functional Materials and Devices

IS - 4

ER -

USB2.0 endpoints controller in 180nm CMOS process

Abstract

Keywords

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