Transmission Line Pulse Induced Breakdown of FinFETs

As a result of the shrinking size of semiconductor circuits, fin field-effect transistors (FinFETs) with better gate control ability become a promising candidate in advanced nanodevices. Enhanced reliability is required for complex three-dimensional conductive channels. Understanding and controlling dielectric breakdown is indispensable to increasing the quality and reliability of advanced devices. In this study, physical failures in FinFET devices induced by electrical overstress (EOS) and electrostatic discharge (ESD) were analyzed by using transmission electron microscopy (TEM) with nanoscale resolution. Two electric technology are direct current (DC) and transmission line pulse (TLP). Interaction between current-temperature positive feedback and dielectric breakdown-induced epitaxy (DBIE) was studied. Under the DC stressing, the Si grew along with three sides of the fin and the dielectric layer was destroyed by the stress. Contrarily, the TLP stress only wore and tore the dielectric layer and the Si grew downwards. The technology computer-aided design (TCAD) simulations show that the breakdown depends on the balance between current-temperature positive feedback and the DBIE mechanism. This work provides guidance for enhancing the reliability of FinFETs.